RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-09 22:04:10 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt

Browse Source 
lowerRangeToAssertZExt currently relies on something like EarlyCSE having
eliminated the constant range [0,1). At -O0 this leads to an assert.

Differential Revision: https://reviews.llvm.org/D53888

llvm-svn: 345770
This commit is contained in:
Scott Linder 2018-10-31 19:57:36 +00:00
parent a377d6ce6a
commit d756c8ad95
2 changed files with 22 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -7993,7 +7993,8 @@ SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
return Op; return Op;
APInt Hi = CR.getUnsignedMax(); APInt Hi = CR.getUnsignedMax();
unsigned Bits = Hi.getActiveBits(); unsigned Bits = std::max(Hi.getActiveBits(),
static_cast<unsigned>(IntegerType::MIN_INT_BITS));
EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);

26
test/CodeGen/AMDGPU/zext-lid.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -march=amdgcn < %s | FileCheck %s ; RUN: llc -march=amdgcn < %s | FileCheck %s
; RUN: llc -O0 -march=amdgcn < %s | FileCheck %s
; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-intrinsics < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-intrinsics < %s | FileCheck -check-prefix=OPT %s
; CHECK-NOT: and_b32 ; CHECK-NOT: and_b32
@ -43,10 +44,21 @@ bb:
ret void ret void
} }
; When EarlyCSE is not run this call produces a range max with 0 active bits,
; which is a special case as an AssertZext from width 0 is invalid.
; OPT-LABEL: @zext_grp_size_1x1x1
; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !4
define amdgpu_kernel void @zext_grp_size_1x1x1(i32 addrspace(1)* nocapture %arg) #0 !reqd_work_group_size !1 {
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = and i32 %tmp, 1
store i32 %tmp1, i32 addrspace(1)* %arg, align 4
ret void
}
; OPT-LABEL: @zext_grp_size_512 ; OPT-LABEL: @zext_grp_size_512
; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !5 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !6
; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !5 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !6
; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !5 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !6
define amdgpu_kernel void @zext_grp_size_512(i32 addrspace(1)* nocapture %arg) #1 { define amdgpu_kernel void @zext_grp_size_512(i32 addrspace(1)* nocapture %arg) #1 {
bb: bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
@ -74,7 +86,7 @@ entry:
} }
; OPT-LABEL: @func_test_workitem_id_x_default_range( ; OPT-LABEL: @func_test_workitem_id_x_default_range(
; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !6 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !7
define void @func_test_workitem_id_x_default_range(i32 addrspace(1)* nocapture %out) #4 { define void @func_test_workitem_id_x_default_range(i32 addrspace(1)* nocapture %out) #4 {
entry: entry:
%id = tail call i32 @llvm.amdgcn.workitem.id.x() %id = tail call i32 @llvm.amdgcn.workitem.id.x()
@ -96,11 +108,13 @@ attributes #3 = { nounwind readnone }
attributes #4 = { nounwind } attributes #4 = { nounwind }
!0 = !{i32 32, i32 4, i32 1} !0 = !{i32 32, i32 4, i32 1}
!1 = !{i32 1, i32 1, i32 1}
; OPT: !0 = !{i32 0, i32 128} ; OPT: !0 = !{i32 0, i32 128}
; OPT: !1 = !{i32 32, i32 4, i32 1} ; OPT: !1 = !{i32 32, i32 4, i32 1}
; OPT: !2 = !{i32 0, i32 32} ; OPT: !2 = !{i32 0, i32 32}
; OPT: !3 = !{i32 0, i32 4} ; OPT: !3 = !{i32 0, i32 4}
; OPT: !4 = !{i32 0, i32 1} ; OPT: !4 = !{i32 0, i32 1}
; OPT: !5 = !{i32 0, i32 512} ; OPT: !5 = !{i32 1, i32 1, i32 1}
; OPT: !6 = !{i32 0, i32 1024} ; OPT: !6 = !{i32 0, i32 512}
; OPT: !7 = !{i32 0, i32 1024}