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[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits.
llvm-svn: 224951
This commit is contained in:
Colin LeMahieu
parent
4e9711a8ac
commit
d92e961fd1
@ -709,9 +709,9 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
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unsigned Opcode = 0;
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// Figure out the post inc version of opcode.
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if (StoredVT == MVT::i64) Opcode = Hexagon::POST_STdri;
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else if (StoredVT == MVT::i32) Opcode = Hexagon::POST_STwri;
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else if (StoredVT == MVT::i16) Opcode = Hexagon::POST_SThri;
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if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
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else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
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else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
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else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
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else llvm_unreachable("unknown memory type");
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@ -1437,8 +1437,8 @@ isConditionalStore (const MachineInstr* MI) const {
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case Hexagon::STrid_indexed_cPt :
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case Hexagon::STrid_indexed_cNotPt :
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case Hexagon::STrid_indexed_shl_cPt_V4 :
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case Hexagon::POST_STdri_cPt :
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case Hexagon::POST_STdri_cNotPt :
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case Hexagon::S2_pstorerdt_pi:
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case Hexagon::S2_pstorerdf_pi:
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case Hexagon::STrih_cPt :
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case Hexagon::STrih_cNotPt :
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case Hexagon::STrih_indexed_cPt :
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@ -1447,8 +1447,8 @@ isConditionalStore (const MachineInstr* MI) const {
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case Hexagon::STrih_imm_cNotPt_V4 :
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case Hexagon::STrih_indexed_shl_cPt_V4 :
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case Hexagon::STrih_indexed_shl_cNotPt_V4 :
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case Hexagon::POST_SThri_cPt :
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case Hexagon::POST_SThri_cNotPt :
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case Hexagon::S2_pstorerht_pi:
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case Hexagon::S2_pstorerhf_pi:
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case Hexagon::STriw_cPt :
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case Hexagon::STriw_cNotPt :
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case Hexagon::STriw_indexed_cPt :
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@ -1457,8 +1457,8 @@ isConditionalStore (const MachineInstr* MI) const {
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case Hexagon::STriw_imm_cNotPt_V4 :
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case Hexagon::STriw_indexed_shl_cPt_V4 :
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case Hexagon::STriw_indexed_shl_cNotPt_V4 :
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case Hexagon::POST_STwri_cPt :
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case Hexagon::POST_STwri_cNotPt :
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case Hexagon::S2_pstorerit_pi:
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case Hexagon::S2_pstorerif_pi:
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return QRI.Subtarget.hasV4TOps();
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// V4 global address store before promoting to dot new.
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@ -2753,55 +2753,17 @@ multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
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let accessSize = ByteAccess, isCodeGenOnly = 0 in
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defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
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//===----------------------------------------------------------------------===//
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// Post increment store
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//===----------------------------------------------------------------------===//
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let accessSize = HalfWordAccess, isCodeGenOnly = 0 in
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defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>;
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multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
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bit isNot, bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2++#$offset) = $src3",
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[],
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"$src2 = $dst">;
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}
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let accessSize = WordAccess, isCodeGenOnly = 0 in
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defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
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multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
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Operand ImmOp, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
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// Predicate new
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let Predicates = [HasV4T], validSubTargets = HasV4SubT in
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defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
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}
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}
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let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
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defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>;
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let hasCtrlDep = 1, isNVStorable = 1, hasSideEffects = 0 in
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multiclass ST_PostInc2<string mnemonic, string BaseOp, RegisterClass RC,
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Operand ImmOp> {
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let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
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let isPredicable = 1 in
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def NAME : STInst2PI<(outs IntRegs:$dst),
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(ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
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mnemonic#"($src1++#$offset) = $src2",
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[],
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"$src1 = $dst">;
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let isPredicated = 1 in {
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defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
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defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
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}
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}
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}
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defm POST_SThri: ST_PostInc2 <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
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defm POST_STwri: ST_PostInc2 <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
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let isNVStorable = 0 in
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defm POST_STdri: ST_PostInc2 <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
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let accessSize = HalfWordAccess, isNVStorable = 0, isCodeGenOnly = 0 in
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defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
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def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
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s4_3ImmPred:$offset),
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@ -2809,14 +2771,14 @@ def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
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def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
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s4_3ImmPred:$offset),
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(POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
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(S2_storerh_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
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def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
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(POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
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(S2_storeri_pi IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
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def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
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s4_3ImmPred:$offset),
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(POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
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(S2_storerd_pi IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
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//===----------------------------------------------------------------------===//
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// multiclass for the store instructions with MEMri operand.
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@ -1,5 +1,18 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0x28 0xd4 0xd1 0xab
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# CHECK: memd(r17++#40) = r21:20
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0x2b 0xf4 0xd1 0xab
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# CHECK: if (p3) memd(r17++#40) = r21:20
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0x2f 0xf4 0xd1 0xab
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# CHECK: if (!p3) memd(r17++#40) = r21:20
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0x03 0x40 0x45 0x85 0xab 0xf4 0xd1 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) memd(r17++#40) = r21:20
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0x03 0x40 0x45 0x85 0xaf 0xf4 0xd1 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memd(r17++#40) = r21:20
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0x28 0xd5 0x11 0xab
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# CHECK: memb(r17++#5) = r21
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0x2b 0xf5 0x11 0xab
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@ -11,4 +24,30 @@
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# CHECK-NEXT: if (p3.new) memb(r17++#5) = r21
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0x03 0x40 0x45 0x85 0xaf 0xf5 0x11 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21
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# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21
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0x28 0xd5 0x51 0xab
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# CHECK: memh(r17++#10) = r21
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0x2b 0xf5 0x51 0xab
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# CHECK: if (p3) memh(r17++#10) = r21
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0x2f 0xf5 0x51 0xab
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# CHECK: if (!p3) memh(r17++#10) = r21
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0x03 0x40 0x45 0x85 0xab 0xf5 0x51 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) memh(r17++#10) = r21
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0x03 0x40 0x45 0x85 0xaf 0xf5 0x51 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21
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0x28 0xd5 0x91 0xab
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# CHECK: memw(r17++#20) = r21
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0x2b 0xf5 0x91 0xab
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# CHECK: if (p3) memw(r17++#20) = r21
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0x2f 0xf5 0x91 0xab
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# CHECK: if (!p3) memw(r17++#20) = r21
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0x03 0x40 0x45 0x85 0xaf 0xf5 0x91 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memw(r17++#20) = r21
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0x03 0x40 0x45 0x85 0xab 0xf5 0x91 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) memw(r17++#20) = r21
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