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[mips] Correct predicates for loads, bit manipulation instructions and some pseudos
Additionally, correct the definition of the rdhwr instruction. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48216 llvm-svn: 335162
This commit is contained in:
Simon Dardis
parent
5622f9d716
commit
d94ff12893
@ -776,7 +776,8 @@ let DecoderNamespace = "MicroMips" in {
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ADD_FM_MM<0, 0x290>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
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ADD_FM_MM<0, 0x310>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
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def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
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MULT_FM_MM<0x22c>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
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@ -1397,6 +1398,10 @@ let EncodingPredicates = [InMicroMips] in {
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def : MipsInstAlias<"j $rs", (JR_MM GPR32Opnd:$rs), 0>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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}
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def : MipsInstAlias<"rdhwr $rt, $rs",
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(RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def : MipsInstAlias<"hypcall", (HYPCALL_MM 0), 1>,
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ISA_MICROMIPS32R5, ASE_VIRT;
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def : MipsInstAlias<"mfgc0 $rt, $rs",
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@ -508,6 +508,7 @@ class EXT_FM<bits<6> funct> : StdArch {
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class RDHWR_FM : StdArch {
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bits<5> rt;
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bits<5> rd;
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bits<3> sel;
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bits<32> Inst;
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@ -515,7 +516,8 @@ class RDHWR_FM : StdArch {
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let Inst{25-21} = 0;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{10-9} = 0b00;
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let Inst{8-6} = sel;
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let Inst{5-0} = 0x3b;
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}
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@ -1824,8 +1824,8 @@ class SubwordSwap<string opstr, RegisterOperand RO,
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// Read Hardware
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class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
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InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
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II_RDHWR, FrmR, "rdhwr">;
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InstSE<(outs CPURegOperand:$rt), (ins RO:$rd, uimm8:$sel),
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"rdhwr\t$rt, $rd, $sel", [], II_RDHWR, FrmR, "rdhwr">;
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// Ext and Ins
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class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
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@ -1834,7 +1834,7 @@ class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
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InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
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!strconcat(opstr, "\t$rt, $rs, $pos, $size"),
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[(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT,
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FrmR, opstr>, ISA_MIPS32R2;
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FrmR, opstr>;
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// 'ins' and its' 64 bit variants are matched by C++ code.
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class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
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@ -1843,7 +1843,7 @@ class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
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!strconcat(opstr, "\t$rt, $rs, $pos, $size"),
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[(set RO:$rt, (null_frag RO:$rs, PosImm:$pos, SizeImm:$size,
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RO:$src))],
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II_INS, FrmR, opstr>, ISA_MIPS32R2 {
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II_INS, FrmR, opstr> {
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let Constraints = "$src = $rt";
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}
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@ -2050,19 +2050,20 @@ let AdditionalPredicates = [NotInMicroMips] in {
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/// aligned
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let AdditionalPredicates = [NotInMicroMips] in {
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def LB : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel,
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LW_FM<0x20>;
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LW_FM<0x20>, ISA_MIPS1;
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def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU,
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addrDefault>, MMRel, LW_FM<0x24>;
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addrDefault>, MMRel, LW_FM<0x24>, ISA_MIPS1;
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def LH : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH,
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addrDefault>, MMRel, LW_FM<0x21>;
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addrDefault>, MMRel, LW_FM<0x21>, ISA_MIPS1;
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def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>,
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MMRel, LW_FM<0x25>;
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MMRel, LW_FM<0x25>, ISA_MIPS1;
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def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
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LW_FM<0x23>;
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LW_FM<0x23>, ISA_MIPS1;
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def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
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LW_FM<0x28>;
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def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
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def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
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LW_FM<0x28>, ISA_MIPS1;
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def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>,
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ISA_MIPS1;
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def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>, ISA_MIPS1;
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}
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/// load/store left/right
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@ -2210,10 +2211,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
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ISA_MIPS1_NOT_32R6_64R6;
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def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,
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BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
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def BAL_BR : BAL_BR_Pseudo<BGEZAL, brtarget>;
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def BAL_BR : BAL_BR_Pseudo<BGEZAL, brtarget>, ISA_MIPS1;
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}
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let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in {
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def TAILCALL : TailCall<J, jmptarget>;
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def TAILCALL : TailCall<J, jmptarget>, ISA_MIPS1;
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}
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let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
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NoIndirectJumpGuards] in
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@ -2357,15 +2358,15 @@ let AdditionalPredicates = [NotInMicroMips] in {
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0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
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def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
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0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
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def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
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def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM, ISA_MIPS1;
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// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
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def EXT : MMRel, StdMMR6Rel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1,
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immZExt5, immZExt5Plus1, MipsExt>,
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EXT_FM<0>;
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EXT_FM<0>, ISA_MIPS32R2;
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def INS : MMRel, StdMMR6Rel, InsBase<"ins", GPR32Opnd, uimm5,
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uimm5_inssize_plus1, immZExt5,
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immZExt5Plus1>,
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EXT_FM<4>;
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EXT_FM<4>, ISA_MIPS32R2;
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}
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/// Move Control Registers From/To CPU Registers
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let AdditionalPredicates = [NotInMicroMips] in {
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@ -2711,6 +2712,9 @@ let AdditionalPredicates = [NotInMicroMips] in {
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(TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
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def : MipsInstAlias<"tne $rs, $rt",
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(TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
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def : MipsInstAlias<"rdhwr $rt, $rs",
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(RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, ISA_MIPS1;
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}
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def : MipsInstAlias<"sub, $rd, $rs, $imm",
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(ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
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@ -976,9 +976,9 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
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}
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SDNode *Rdhwr =
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CurDAG->getMachineNode(RdhwrOpc, DL,
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Node->getValueType(0),
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CurDAG->getRegister(Mips::HWR29, MVT::i32));
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CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0),
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CurDAG->getRegister(Mips::HWR29, MVT::i32),
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CurDAG->getTargetConstant(0, DL, MVT::i32));
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SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
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SDValue(Rdhwr, 0));
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SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
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@ -157,7 +157,7 @@ body: |
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%0 = ADDu killed %8, killed %14
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%15 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
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%16 = DADDiu killed %15, target-flags(mips-tprel-lo) @__tls_guard
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%17 = RDHWR64 $hwr29
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%17 = RDHWR64 $hwr29, 0
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$v1_64 = COPY %17
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%18 = COPY $v1_64
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%19 = DADDu %18, killed %16
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@ -170,7 +170,7 @@ body: |
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%32 = LUi64 target-flags(mips-tprel-hi) @k
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%33 = DADDiu killed %32, target-flags(mips-tprel-lo) @k
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%34 = RDHWR64 $hwr29
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%34 = RDHWR64 $hwr29, 0
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$v1_64 = COPY %34
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%35 = COPY $v1_64
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%36 = DADDu %35, killed %33
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@ -182,7 +182,7 @@ body: |
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%21 = LUi64 target-flags(mips-tprel-hi) @__tls_guard
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%22 = DADDiu killed %21, target-flags(mips-tprel-lo) @__tls_guard
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%23 = RDHWR64 $hwr29
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%23 = RDHWR64 $hwr29, 0
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$v1_64 = COPY %23
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%24 = COPY $v1_64
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%25 = DADDu %24, killed %22
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@ -222,7 +222,7 @@ body: |
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ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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bb.5._ZTW1j.exit:
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%44 = RDHWR64 $hwr29
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%44 = RDHWR64 $hwr29, 0
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$v1_64 = COPY %44
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%45 = LD %43, target-flags(mips-gottprel) @j :: (load 8)
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%46 = COPY $v1_64
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@ -131,6 +131,7 @@ ori $9, $6, 17767 # CHECK: ori $9, $6, 17767 # encoding: [0x51,0x
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xor $3, $3, $5 # CHECK: xor $3, $3, $5 # encoding: [0x00,0xa3,0x1b,0x10]
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xori $9, $6, 17767 # CHECK: xori $9, $6, 17767 # encoding: [0x71,0x26,0x45,0x67]
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nor $9, $6, $7 # CHECK: nor $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0xd0]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} NOR_MM
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not $7, $8 # CHECK: not $7, $8 # encoding: [0x00,0x08,0x3a,0xd0]
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not $7 # CHECK: not $7, $7 # encoding: [0x00,0x07,0x3a,0xd0]
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mul $9, $6, $7 # CHECK: mul $9, $6, $7 # encoding: [0x00,0xe6,0x4a,0x10]
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@ -142,6 +143,12 @@ div $zero, $9, $7 # CHECK: div $zero, $9, $7 # encoding: [0x00,0x
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div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x01,0xf0]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} FDIV_D32_MM
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divu $zero, $9, $7 # CHECK: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c]
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rdhwr $5, $29, 2 # CHECK: rdhwr $5, $29, 2 # encoding: [0x00,0xbd,0x6b,0x3c]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} RDHWR_MM
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rdhwr $5, $29, 0 # CHECK: rdhwr $5, $29 # encoding: [0x00,0xbd,0x6b,0x3c]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} RDHWR_MM
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rdhwr $5, $29 # CHECK: rdhwr $5, $29 # encoding: [0x00,0xbd,0x6b,0x3c]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} RDHWR_MM
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sll $4, $3, 7 # CHECK: sll $4, $3, 7 # encoding: [0x00,0x83,0x38,0x00]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL_MM
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sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
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@ -157,15 +164,25 @@ srlv $2, $3, $5 # CHECK: srlv $2, $3, $5 # encoding: [0x00,0x
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rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
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rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
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lb $5, 8($4) # CHECK: lb $5, 8($4) # encoding: [0x1c,0xa4,0x00,0x08]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} LB_MM
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lbu $6, 8($4) # CHECK: lbu $6, 8($4) # encoding: [0x14,0xc4,0x00,0x08]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} LBu_MM
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lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} LH_MM
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lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} LHu_MM
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lw $6, 4($5) # CHECK: lw $6, 4($5) # encoding: [0xfc,0xc5,0x00,0x04]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} LW_MM
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lw $6, 123($sp) # CHECK: lw $6, 123($sp) # encoding: [0xfc,0xdd,0x00,0x7b]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} LW_MM
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sb $5, 8($4) # CHECK: sb $5, 8($4) # encoding: [0x18,0xa4,0x00,0x08]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SB_MM
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sh $2, 8($4) # CHECK: sh $2, 8($4) # encoding: [0x38,0x44,0x00,0x08]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SH_MM
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sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SW_MM
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sw $5, 123($sp) # CHECK: sw $5, 123($sp) # encoding: [0xf8,0xbd,0x00,0x7b]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SW_MM
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lwu $2, 8($4) # CHECK: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08]
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lwl $4, 16($5) # CHECK: lwl $4, 16($5) # encoding: [0x60,0x85,0x00,0x10]
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lwr $4, 16($5) # CHECK: lwr $4, 16($5) # encoding: [0x60,0x85,0x10,0x10]
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@ -82,7 +82,9 @@
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lapc $7, 1048572 # CHECK: lapc $7, 1048572 # encoding: [0x78,0xe3,0xff,0xff]
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lapc $7, -1048576 # CHECK: lapc $7, -1048576 # encoding: [0x78,0xe4,0x00,0x00]
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lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
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# CHECK-NEXT: # <MCInst #{{.*}} LH_MM
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lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
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# CHECK-NEXT: # <MCInst #{{.*}} LHu_MM
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lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f]
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lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
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lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
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@ -124,6 +126,7 @@
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muhu $3, $4, $5 # CHECK: muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
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nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0]
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# CHECK-NEXT: # <MCInst #{{.*}} NOR_MMR6
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or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]
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ori $3, $4, 1234 # CHECK: ori $3, $4, 1234 # encoding: [0x50,0x64,0x04,0xd2]
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pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
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@ -143,6 +146,7 @@
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subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]
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sw $4, 124($sp) # CHECK: sw $4, 124($sp) # encoding: [0xc8,0x9f]
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sw $4, 128($sp) # CHECK: sw $4, 128($sp) # encoding: [0xf8,0x9d,0x00,0x80]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} SW_MMR6
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sw16 $4, 4($17) # CHECK: sw16 $4, 4($17) # encoding: [0xea,0x11]
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sw16 $0, 4($17) # CHECK: sw16 $zero, 4($17) # encoding: [0xe8,0x11]
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swm $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
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@ -151,8 +155,11 @@
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wsbh $3, $4 # CHECK: wsbh $3, $4 # encoding: [0x00,0x64,0x7b,0x3c]
|
||||
pause # CHECK: pause # encoding: [0x00,0x00,0x28,0x00]
|
||||
rdhwr $5, $29, 2 # CHECK: rdhwr $5, $29, 2 # encoding: [0x00,0xbd,0x11,0xc0]
|
||||
# CHECK-NEXT: # <MCInst #{{[0-9]+}} RDHWR_MMR6
|
||||
rdhwr $5, $29, 0 # CHECK: rdhwr $5, $29 # encoding: [0x00,0xbd,0x01,0xc0]
|
||||
# CHECK-NEXT: # <MCInst #{{[0-9]+}} RDHWR_MMR6
|
||||
rdhwr $5, $29 # CHECK: rdhwr $5, $29 # encoding: [0x00,0xbd,0x01,0xc0]
|
||||
# CHECK-NEXT: # <MCInst #{{[0-9]+}} RDHWR_MMR6
|
||||
wait # CHECK: wait # encoding: [0x00,0x00,0x93,0x7c]
|
||||
wait 17 # CHECK: wait 17 # encoding: [0x00,0x11,0x93,0x7c]
|
||||
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x08,0x00]
|
||||
@ -276,7 +283,9 @@
|
||||
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
|
||||
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
|
||||
sb $4, 6($5) # CHECK: sb $4, 6($5) # encoding: [0x18,0x85,0x00,0x06]
|
||||
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SB_MMR6
|
||||
sh $4, 6($5) # CHECK: sh $4, 6($5) # encoding: [0x38,0x85,0x00,0x06]
|
||||
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SH_MMR6
|
||||
lw $4, 6($5) # CHECK: lw $4, 6($5) # encoding: [0xfc,0x85,0x00,0x06]
|
||||
lui $6, 17767 # CHECK: lui $6, 17767 # encoding: [0x10,0xc0,0x45,0x67]
|
||||
addu16 $6, $17, $4 # CHECK: addu16 $6, $17, $4 # encoding: [0x04,0xcc]
|
||||
@ -305,7 +314,9 @@
|
||||
subu16 $5, $16, $3 # CHECK: subu16 $5, $16, $3 # encoding: [0x04,0x3b]
|
||||
xor16 $17, $5 # CHECK: xor16 $17, $5 # encoding: [0x44,0xd8]
|
||||
lb $4, 8($5) # CHECK: lb $4, 8($5) # encoding: [0x1c,0x85,0x00,0x08]
|
||||
# CHECK-NEXT: # <MCInst #{{[0-9]+}} LB_MMR6
|
||||
lbu $4, 8($5) # CHECK: lbu $4, 8($5) # encoding: [0x14,0x85,0x00,0x08]
|
||||
# CHECK-NEXT: # <MCInst #{{[0-9]+}} LBU_MMR6
|
||||
recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x44,0x12,0x3b]
|
||||
recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b]
|
||||
rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x54,0x82,0x00,0x20]
|
||||
|
||||
@ -9,3 +9,5 @@
|
||||
di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ext $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ins $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
@ -98,3 +98,5 @@
|
||||
suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ext $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ins $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
@ -9,3 +9,5 @@
|
||||
di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ext $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ins $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
@ -34,3 +34,5 @@
|
||||
suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ext $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ins $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
@ -9,3 +9,5 @@
|
||||
di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ext $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ins $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
@ -9,3 +9,5 @@
|
||||
di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ext $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ins $1, $2, 4, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
Loading…
Reference in New Issue
Block a user