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[DAG] Factor out common expressions. NFC.

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llvm-svn: 309740
This commit is contained in:
Nirav Dave 2017-08-01 20:30:52 +00:00
parent e36216c004
commit d961d16bde
1 changed files with 21 additions and 19 deletions
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40
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -12550,6 +12550,7 @@ void DAGCombiner::getStoreMergeCandidates(
BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr(), DAG);
EVT MemVT = St->getMemoryVT();
SDValue Val = St->getValue();
// We must have a base and an offset.
if (!BasePtr.getBase().getNode())
return;
@ -12558,17 +12559,15 @@ void DAGCombiner::getStoreMergeCandidates(
if (BasePtr.getBase().isUndef())
return;
bool IsConstantSrc = isa<ConstantSDNode>(St->getValue()) ||
isa<ConstantFPSDNode>(St->getValue());
bool IsExtractVecSrc =
(St->getValue().getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
St->getValue().getOpcode() == ISD::EXTRACT_SUBVECTOR);
bool IsLoadSrc = isa<LoadSDNode>(St->getValue());
bool IsConstantSrc = isa<ConstantSDNode>(Val) || isa<ConstantFPSDNode>(Val);
bool IsExtractVecSrc = (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
Val.getOpcode() == ISD::EXTRACT_SUBVECTOR);
bool IsLoadSrc = isa<LoadSDNode>(Val);
BaseIndexOffset LBasePtr;
// Match on loadbaseptr if relevant.
EVT LoadVT;
if (IsLoadSrc) {
auto *Ld = cast<LoadSDNode>(St->getValue());
auto *Ld = cast<LoadSDNode>(Val);
LBasePtr = BaseIndexOffset::match(Ld->getBasePtr(), DAG);
LoadVT = Ld->getMemoryVT();
// Load and store should be the same type.
@ -12579,14 +12578,15 @@ void DAGCombiner::getStoreMergeCandidates(
int64_t &Offset) -> bool {
if (Other->isVolatile() || Other->isIndexed())
return false;
SDValue Val = Other->getValue();
// We can merge constant floats to equivalent integers
if (Other->getMemoryVT() != MemVT)
if (!(MemVT.isInteger() && MemVT.bitsEq(Other->getMemoryVT()) &&
isa<ConstantFPSDNode>(Other->getValue())))
isa<ConstantFPSDNode>(Val)))
return false;
if (IsLoadSrc) {
// The Load's Base Ptr must also match
if (LoadSDNode *OtherLd = dyn_cast<LoadSDNode>(Other->getValue())) {
if (LoadSDNode *OtherLd = dyn_cast<LoadSDNode>(Val)) {
auto LPtr = BaseIndexOffset::match(OtherLd->getBasePtr(), DAG);
if (LoadVT != OtherLd->getMemoryVT())
return false;
@ -12595,14 +12595,15 @@ void DAGCombiner::getStoreMergeCandidates(
} else
return false;
}
if (IsConstantSrc)
if (!(isa<ConstantSDNode>(Other->getValue()) ||
isa<ConstantFPSDNode>(Other->getValue())))
if (IsConstantSrc) {
if (!(isa<ConstantSDNode>(Val) || isa<ConstantFPSDNode>(Val)))
return false;
if (IsExtractVecSrc)
if (!(Other->getValue().getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
Other->getValue().getOpcode() == ISD::EXTRACT_SUBVECTOR))
}
if (IsExtractVecSrc) {
if (!(Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
Val.getOpcode() == ISD::EXTRACT_SUBVECTOR))
return false;
}
Ptr = BaseIndexOffset::match(Other->getBasePtr(), DAG);
return (BasePtr.equalBaseIndex(Ptr, DAG, Offset));
};
@ -12876,14 +12877,14 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
unsigned NumStoresToMerge = 1;
for (unsigned i = 0; i < NumConsecutiveStores; ++i) {
StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
unsigned StoreValOpcode = St->getValue().getOpcode();
SDValue StVal = St->getValue();
// This restriction could be loosened.
// Bail out if any stored values are not elements extracted from a
// vector. It should be possible to handle mixed sources, but load
// sources need more careful handling (see the block of code below that
// handles consecutive loads).
if (StoreValOpcode != ISD::EXTRACT_VECTOR_ELT &&
StoreValOpcode != ISD::EXTRACT_SUBVECTOR)
if (StVal.getOpcode() != ISD::EXTRACT_VECTOR_ELT &&
StVal.getOpcode() != ISD::EXTRACT_SUBVECTOR)
return RV;
// Find a legal type for the vector store.
@ -12925,7 +12926,8 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
BaseIndexOffset LdBasePtr;
for (unsigned i = 0; i < NumConsecutiveStores; ++i) {
StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
SDValue Val = St->getValue();
LoadSDNode *Ld = dyn_cast<LoadSDNode>(Val);
if (!Ld)
break;