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Assembly parsing for 4-register sequential variant of VLD2.

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llvm-svn: 142704
This commit is contained in:
Jim Grosbach 2011-10-21 23:58:57 +00:00
parent a6e536367e
commit d964cf8939
4 changed files with 24 additions and 42 deletions
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12
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -181,12 +181,12 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
{ ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 ,false},
{ ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 ,false},
{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 ,true},
{ ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 ,true},
{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 ,true},
{ ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 ,true},
{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 ,true},
{ ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 ,true},
{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 ,false},
{ ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 ,false},
{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 ,false},
{ ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 ,false},
{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 ,false},
{ ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 ,false},
{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, SingleSpc, 3, 4,true},
{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, SingleSpc, 3, 4,true},

24
lib/Target/ARM/ARMInstrNEON.td
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@ -411,11 +411,11 @@ class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDInstruction";
}
class VLD2Q<bits<4> op7_4, string Dt>
class VLD2Q<bits<4> op7_4, string Dt, RegisterOperand VdTy>
: NLdSt<0, 0b10, 0b0011, op7_4,
(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
(outs VdTy:$Vd),
(ins addrmode6:$Rn), IIC_VLD2x2,
"vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
"vld2", Dt, "$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDInstruction";
@ -425,9 +425,9 @@ def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8", VecListTwoD>;
def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16", VecListTwoD>;
def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32", VecListTwoD>;
def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
def VLD2q8 : VLD2Q<{0,0,?,?}, "8", VecListFourD>;
def VLD2q16 : VLD2Q<{0,1,?,?}, "16", VecListFourD>;
def VLD2q32 : VLD2Q<{1,0,?,?}, "32", VecListFourD>;
def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
@ -446,11 +446,11 @@ class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy>
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDInstruction";
}
class VLD2QWB<bits<4> op7_4, string Dt>
class VLD2QWB<bits<4> op7_4, string Dt, RegisterOperand VdTy>
: NLdSt<0, 0b10, 0b0011, op7_4,
(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
(outs VdTy:$Vd, GPR:$wb),
(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
"vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
"vld2", Dt, "$Vd, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDInstruction";
@ -460,9 +460,9 @@ def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8", VecListFourD>;
def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16", VecListFourD>;
def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32", VecListFourD>;
def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;

18
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -1959,12 +1959,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
// Second output register
switch (Inst.getOpcode()) {
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8_UPD:
case ARM::VLD2q16_UPD:
case ARM::VLD2q32_UPD:
case ARM::VLD3d8:
case ARM::VLD3d16:
case ARM::VLD3d32:
@ -2006,12 +2000,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
// Third output register
switch(Inst.getOpcode()) {
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8_UPD:
case ARM::VLD2q16_UPD:
case ARM::VLD2q32_UPD:
case ARM::VLD3d8:
case ARM::VLD3d16:
case ARM::VLD3d32:
@ -2048,12 +2036,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
// Fourth output register
switch (Inst.getOpcode()) {
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32:
case ARM::VLD2q8_UPD:
case ARM::VLD2q16_UPD:
case ARM::VLD2q32_UPD:
case ARM::VLD4d8:
case ARM::VLD4d16:
case ARM::VLD4d32:

12
test/MC/ARM/neon-vld-encoding.s
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@ -38,16 +38,16 @@
vld2.8 {d16, d17}, [r0, :64]
vld2.16 {d16, d17}, [r0, :128]
vld2.32 {d16, d17}, [r0]
@ vld2.8 {d16, d17, d18, d19}, [r0, :64]
@ vld2.16 {d16, d17, d18, d19}, [r0, :128]
@ vld2.32 {d16, d17, d18, d19}, [r0, :256]
vld2.8 {d16, d17, d18, d19}, [r0, :64]
vld2.16 {d16, d17, d18, d19}, [r0, :128]
vld2.32 {d16, d17, d18, d19}, [r0, :256]
@ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4]
@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4]
@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4]
@ FIXME: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4]
@ FIXME: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4]
@ FIXME: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4]
@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4]
@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4]
@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4]
@ vld3.8 {d16, d17, d18}, [r0, :64]