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[PowerPC][MC] Support expressions in getMemRIX16Encoding.

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Loosens an assert in getMemRIX16Encoding that restricts DQ-form instructions to
using an immediate, so that we can assemble instructions like lxv/stxv where the
offset is an expression.

Differential Revision: https://reviews.llvm.org/D51122

llvm-svn: 340761
This commit is contained in:
Sean Fertile 2018-08-27 17:37:43 +00:00
parent bc59f97bc1
commit da4254727a
2 changed files with 47 additions and 3 deletions
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12
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View File

@ -264,10 +264,16 @@ unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
const MCOperand &MO = MI.getOperand(OpNo);
assert(MO.isImm() && !(MO.getImm() % 16) &&
"Expecting an immediate that is a multiple of 16");
if (MO.isImm()) {
assert(!(MO.getImm() % 16) &&
"Expecting an immediate that is a multiple of 16");
return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
}
return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
// Otherwise add a fixup for the displacement field.
Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_half16ds));
return RegBits;
}
unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,

38
test/MC/PowerPC/ppc64-dq-expr.s Normal file
View File

@ -0,0 +1,38 @@
# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu %s -filetype=obj -o - | \
# RUN: llvm-objdump -D -r - | FileCheck %s
.text
.abiversion 2
.global test
.p2align 4
.type test,@function
test:
.Lgep:
addis 2, 12, .TOC.-.Lgep@ha
addi 2, 2, .TOC.-.Lgep@l
.Llep:
.localentry test, .Llep-.Lgep
addis 3, 2, vecA@toc@ha
lxv 3, vecA@toc@l(3)
addis 3, 2, vecB@toc@ha
stxv 3, vecB@toc@l(3)
blr
.comm vecA, 16, 16
.comm vecB, 16, 16
# CHECK: Disassembly of section .text:
# CHECK-LABEL: test:
# CHECK-NEXT: addis 2, 12, 0
# CHECK-NEXT: R_PPC64_REL16_HA .TOC.
# CHECK-NEXT: addi 2, 2, 0
# CHECK-NEXT: R_PPC64_REL16_LO .TOC.
# CHECK-NEXT: addis 3, 2, 0
# CHECK-NEXT: R_PPC64_TOC16_HA vecA
# CHECK-NEXT: lxv 3, 0(3)
# CHECK-NEXT: R_PPC64_TOC16_LO_DS vecA
# CHECK-NEXT: addis 3, 2, 0
# CHECK-NEXT: R_PPC64_TOC16_HA vecB
# CHECK-NEXT: stxv 3, 0(3)
# CHECK-NEXT: R_PPC64_TOC16_LO_DS vecB
# CHECK-NEXT: blr