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Fix lowering of INSERT_VECTOR_ELT in SPU.

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The IDX was treated as byte index, not element index.

llvm-svn: 112422
This commit is contained in:
Kalle Raiskila 2010-08-29 12:41:50 +00:00
parent 8a7258d771
commit daba4ffc75
2 changed files with 12 additions and 3 deletions
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7
lib/Target/CellSPU/SPUISelLowering.cpp
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@ -2053,20 +2053,21 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
SDValue IdxOp = Op.getOperand(2);
DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType();
EVT eltVT = ValOp.getValueType();
// use 0 when the lane to insert to is 'undef'
int64_t Idx=0;
int64_t Offset=0;
if (IdxOp.getOpcode() != ISD::UNDEF) {
ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
Idx = (CN->getSExtValue());
Offset = (CN->getSExtValue()) * eltVT.getSizeInBits()/8;
}
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Use $sp ($1) because it's always 16-byte aligned and it's available:
SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
DAG.getRegister(SPU::R1, PtrVT),
DAG.getConstant(Idx, PtrVT));
DAG.getConstant(Offset, PtrVT));
// widen the mask when dealing with half vectors
EVT maskVT = EVT::getVectorVT(*(DAG.getContext()), VT.getVectorElementType(),
128/ VT.getVectorElementType().getSizeInBits());

8
test/CodeGen/CellSPU/shuffles.ll
View File

@ -31,3 +31,11 @@ define void @test_insert( <2 x float>* %ptr, float %val1, float %val2 ) {
ret void
}
define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) {
;CHECK: cwd $5, 4($sp)
;CHECK: shufb $3, $4, $3, $5
;CHECK: bi $lr
%rv = insertelement <4 x float> %vparam, float %eltparam, i32 1
ret <4 x float> %rv
}