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remove various std::ostream version of printing methods from

Browse Source 
MachineInstr and MachineOperand.  This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)

llvm-svn: 79813
This commit is contained in:
Chris Lattner 2009-08-23 03:41:05 +00:00
parent 11e35ba9c2
commit db2965c71f
19 changed files with 78 additions and 118 deletions
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14
include/llvm/CodeGen/MachineInstr.h
View File

@ -292,16 +292,7 @@ public:
//
// Debugging support
//
void print(std::ostream *OS, const TargetMachine *TM) const {
if (OS) print(*OS, TM);
}
void print(std::ostream &OS, const TargetMachine *TM = 0) const;
void print(std::ostream *OS) const { if (OS) print(*OS); }
void print(raw_ostream *OS, const TargetMachine *TM) const {
if (OS) print(*OS, TM);
}
void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
void print(raw_ostream *OS) const { if (OS) print(*OS); }
void dump() const;
//===--------------------------------------------------------------------===//
@ -360,11 +351,6 @@ private:
//===----------------------------------------------------------------------===//
// Debugging Support
inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) {
MI.print(OS);
return OS;
}
inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
MI.print(OS);
return OS;

7
include/llvm/CodeGen/MachineOperand.h
View File

@ -16,7 +16,6 @@
#include "llvm/Support/DataTypes.h"
#include <cassert>
#include <iosfwd>
namespace llvm {
@ -133,7 +132,6 @@ public:
MachineInstr *getParent() { return ParentMI; }
const MachineInstr *getParent() const { return ParentMI; }
void print(std::ostream &os, const TargetMachine *TM = 0) const;
void print(raw_ostream &os, const TargetMachine *TM = 0) const;
//===--------------------------------------------------------------------===//
@ -468,11 +466,6 @@ private:
void RemoveRegOperandFromRegInfo();
};
inline std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
MO.print(OS, 0);
return OS;
}
inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) {
MO.print(OS, 0);
return OS;

4
lib/CodeGen/IfConversion.cpp
View File

@ -1133,7 +1133,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
continue;
if (!TII->PredicateInstruction(I, Cond)) {
#ifndef NDEBUG
cerr << "Unable to predicate " << *I << "!\n";
errs() << "Unable to predicate " << *I << "!\n";
#endif
llvm_unreachable(0);
}
@ -1169,7 +1169,7 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
if (!isPredicated)
if (!TII->PredicateInstruction(MI, Cond)) {
#ifndef NDEBUG
cerr << "Unable to predicate " << *I << "!\n";
errs() << "Unable to predicate " << *I << "!\n";
#endif
llvm_unreachable(0);
}

14
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -517,19 +517,21 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
/// print - Implement the dump method.
void LiveIntervals::print(std::ostream &O, const Module* ) const {
O << "********** INTERVALS **********\n";
raw_os_ostream OS(O);
OS << "********** INTERVALS **********\n";
for (const_iterator I = begin(), E = end(); I != E; ++I) {
I->second->print(O, tri_);
O << "\n";
I->second->print(OS, tri_);
OS << "\n";
}
O << "********** MACHINEINSTRS **********\n";
OS << "********** MACHINEINSTRS **********\n";
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) {
O << ((Value*)mbbi->getBasicBlock())->getNameStr() << ":\n";
OS << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
for (MachineBasicBlock::iterator mii = mbbi->begin(),
mie = mbbi->end(); mii != mie; ++mii) {
O << getInstructionIndex(mii) << '\t' << *mii;
OS << getInstructionIndex(mii) << '\t' << *mii;
}
}
}

12
lib/CodeGen/LiveVariables.cpp
View File

@ -52,17 +52,17 @@ void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
}
void LiveVariables::VarInfo::dump() const {
cerr << " Alive in blocks: ";
errs() << " Alive in blocks: ";
for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
E = AliveBlocks.end(); I != E; ++I)
cerr << *I << ", ";
cerr << "\n Killed by:";
errs() << *I << ", ";
errs() << "\n Killed by:";
if (Kills.empty())
cerr << " No instructions.\n";
errs() << " No instructions.\n";
else {
for (unsigned i = 0, e = Kills.size(); i != e; ++i)
cerr << "\n #" << i << ": " << *Kills[i];
cerr << "\n";
errs() << "\n #" << i << ": " << *Kills[i];
errs() << "\n";
}
}

12
lib/CodeGen/MachineInstr.cpp
View File

@ -183,11 +183,6 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
/// print - Print the specified machine operand.
///
void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
raw_os_ostream RawOS(OS);
print(RawOS, TM);
}
void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
switch (getType()) {
case MachineOperand::MO_Register:
@ -948,12 +943,7 @@ bool MachineInstr::hasVolatileMemoryRef() const {
}
void MachineInstr::dump() const {
cerr << " " << *this;
}
void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
raw_os_ostream RawOS(OS);
print(RawOS, TM);
errs() << " " << *this;
}
void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {

2
lib/CodeGen/MachineVerifier.cpp
View File

@ -254,7 +254,7 @@ MachineVerifier::report(const char *msg, const MachineInstr *MI)
assert(MI);
report(msg, MI->getParent());
*OS << "- instruction: ";
MI->print(OS, TM);
MI->print(*OS, TM);
}
void

8
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -259,7 +259,7 @@ unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
else {
#ifndef NDEBUG
cerr << MO;
errs() << MO;
#endif
llvm_unreachable(0);
}
@ -336,7 +336,7 @@ void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
template<class CodeEmitter>
void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
MCE.processDebugLoc(MI.getDebugLoc());
@ -418,8 +418,8 @@ void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
ARMConstantPoolValue *ACPV =
static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
DOUT << " ** ARM constant pool #" << CPI << " @ "
<< (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
<< (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
GlobalValue *GV = ACPV->getGV();
if (GV) {

29
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -27,6 +27,7 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Statistic.h"
@ -771,11 +772,11 @@ bool ARMConstantIslands::CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
assert(CPEOffset%4 == 0 && "Misaligned CPE");
if (DoDump) {
DOUT << "User of CPE#" << CPEMI->getOperand(0).getImm()
<< " max delta=" << MaxDisp
<< " insn address=" << UserOffset
<< " CPE address=" << CPEOffset
<< " offset=" << int(CPEOffset-UserOffset) << "\t" << *MI;
DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
<< " max delta=" << MaxDisp
<< " insn address=" << UserOffset
<< " CPE address=" << CPEOffset
<< " offset=" << int(CPEOffset-UserOffset) << "\t" << *MI);
}
return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
@ -1148,7 +1149,8 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &MF,
break;
}
DOUT << " Moved CPE to #" << ID << " CPI=" << CPI << "\t" << *UserMI;
DEBUG(errs() << " Moved CPE to #" << ID << " CPI=" << CPI
<< '\t' << *UserMI);
return true;
}
@ -1204,11 +1206,11 @@ bool ARMConstantIslands::BBIsInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
unsigned BrOffset = GetOffsetOf(MI) + PCAdj;
unsigned DestOffset = BBOffsets[DestBB->getNumber()];
DOUT << "Branch of destination BB#" << DestBB->getNumber()
<< " from BB#" << MI->getParent()->getNumber()
<< " max delta=" << MaxDisp
<< " from " << GetOffsetOf(MI) << " to " << DestOffset
<< " offset " << int(DestOffset-BrOffset) << "\t" << *MI;
DEBUG(errs() << "Branch of destination BB#" << DestBB->getNumber()
<< " from BB#" << MI->getParent()->getNumber()
<< " max delta=" << MaxDisp
<< " from " << GetOffsetOf(MI) << " to " << DestOffset
<< " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
if (BrOffset <= DestOffset) {
// Branch before the Dest.
@ -1255,7 +1257,7 @@ ARMConstantIslands::FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br) {
HasFarJump = true;
NumUBrFixed++;
DOUT << " Changed B to long jump " << *MI;
DEBUG(errs() << " Changed B to long jump " << *MI);
return true;
}
@ -1299,7 +1301,8 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br) {
// b L1
MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
if (BBIsInRange(MI, NewDest, Br.MaxDisp)) {
DOUT << " Invert Bcc condition and swap its destination with " << *BMI;
DEBUG(errs() << " Invert Bcc condition and swap its destination with "
<< *BMI);
BMI->getOperand(0).setMBB(DestBB);
MI->getOperand(0).setMBB(NewDest);
MI->getOperand(1).setImm(CC);

7
lib/Target/ARM/ARMConstantPoolValue.cpp
View File

@ -15,7 +15,6 @@
#include "llvm/ADT/FoldingSet.h"
#include "llvm/GlobalValue.h"
#include "llvm/Type.h"
#include "llvm/Support/Streams.h"
#include "llvm/Support/raw_ostream.h"
#include <cstdlib>
using namespace llvm;
@ -81,13 +80,9 @@ ARMConstantPoolValue::AddSelectionDAGCSEId(FoldingSetNodeID &ID) {
}
void ARMConstantPoolValue::dump() const {
cerr << " " << *this;
errs() << " " << *this;
}
void ARMConstantPoolValue::print(std::ostream &O) const {
raw_os_ostream RawOS(O);
print(RawOS);
}
void ARMConstantPoolValue::print(raw_ostream &O) const {
if (GV)

8
lib/Target/ARM/ARMConstantPoolValue.h
View File

@ -15,7 +15,6 @@
#define LLVM_TARGET_ARM_CONSTANTPOOLVALUE_H
#include "llvm/CodeGen/MachineConstantPool.h"
#include <iosfwd>
namespace llvm {
@ -80,18 +79,11 @@ public:
virtual void AddSelectionDAGCSEId(FoldingSetNodeID &ID);
void print(std::ostream *O) const { if (O) print(*O); }
void print(std::ostream &O) const;
void print(raw_ostream *O) const { if (O) print(*O); }
void print(raw_ostream &O) const;
void dump() const;
};
inline std::ostream &operator<<(std::ostream &O,
const ARMConstantPoolValue &V) {
V.print(O);
return O;
}
inline raw_ostream &operator<<(raw_ostream &O, const ARMConstantPoolValue &V) {
V.print(O);

7
lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@ -19,6 +19,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/Statistic.h"
using namespace llvm;
@ -353,7 +354,7 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
MIB.addOperand(MI->getOperand(OpNum));
DOUT << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB;
DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
MBB.erase(MI);
++NumLdSts;
@ -471,7 +472,7 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
MIB.addOperand(MI->getOperand(i));
}
DOUT << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB;
DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
MBB.erase(MI);
++Num2Addrs;
@ -571,7 +572,7 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
if (!TID.isPredicable() && NewTID.isPredicable())
AddDefaultPred(MIB);
DOUT << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB;
DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
MBB.erase(MI);
++NumNarrows;

6
lib/Target/Alpha/AlphaCodeEmitter.cpp
View File

@ -170,7 +170,7 @@ static unsigned getAlphaRegNumber(unsigned Reg) {
}
unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) {
const MachineOperand &MO) {
unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
@ -180,7 +180,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
} else if (MO.isImm()) {
rv = MO.getImm();
} else if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
DOUT << MO << " is a relocated op for " << MI << "\n";
DEBUG(errs() << MO << " is a relocated op for " << MI << "\n");
unsigned Reloc = 0;
int Offset = 0;
bool useGOT = false;
@ -235,7 +235,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
Alpha::reloc_bsr, MO.getMBB()));
} else {
#ifndef NDEBUG
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
#endif
llvm_unreachable(0);
}

12
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -362,21 +362,21 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
"Instr doesn't have FrameIndex operand!");
}
#ifndef NDEBUG
#ifndef NDEBUG
DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n");
DOUT << "<--------->\n";
MI.print(DOUT);
#endif
DEBUG(errs() << "<--------->\n");
DEBUG(MI.print(errs()));
#endif
int FrameIndex = MI.getOperand(i).getIndex();
int stackSize = MF.getFrameInfo()->getStackSize();
int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
#ifndef NDEBUG
#ifndef NDEBUG
DOUT << "FrameIndex : " << FrameIndex << "\n";
DOUT << "spOffset : " << spOffset << "\n";
DOUT << "stackSize : " << stackSize << "\n";
#endif
#endif
// as explained on LowerFormalArguments, detect negative offsets
// and adjust SPOffsets considering the final stack size.

5
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -58,8 +58,7 @@ namespace {
template <class CodeEmitter>
class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
public PPCCodeEmitter
{
public PPCCodeEmitter {
TargetMachine &TM;
CodeEmitter &MCE;
@ -267,7 +266,7 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
Reloc, MO.getMBB()));
} else {
#ifndef NDEBUG
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
errs() << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
#endif
llvm_unreachable(0);
}

5
lib/Target/Sparc/FPMover.cpp
View File

@ -21,6 +21,7 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
STATISTIC(NumFpDs , "Number of instructions translated");
@ -113,12 +114,12 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
MI->getOperand(0).setReg(EvenDestReg);
MI->getOperand(1).setReg(EvenSrcReg);
DOUT << "FPMover: the modified instr is: " << *MI;
DEBUG(errs() << "FPMover: the modified instr is: " << *MI);
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {
MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
.addReg(OddSrcReg);
DOUT << "FPMover: the inserted instr is: " << *MI;
DEBUG(errs() << "FPMover: the inserted instr is: " << *MI);
}
++NumFpDs;
}

6
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -275,13 +275,13 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
DEBUG(
MachineBasicBlock::iterator PrevI(PrevMI);
if (I == PrevI) {
cerr << "Just deleted pseudo instruction\n";
errs() << "Just deleted pseudo instruction\n";
} else {
MachineBasicBlock::iterator Start = I;
// Rewind to first instruction newly inserted.
while (Start != BB.begin() && prior(Start) != PrevI) --Start;
cerr << "Inserted instructions:\n\t";
Start->print(*cerr.stream(), &MF.getTarget());
errs() << "Inserted instructions:\n\t";
Start->print(errs(), &MF.getTarget());
while (++Start != next(I)) {}
}
dumpStack();

28
lib/Target/X86/X86InstrInfo.cpp
View File

@ -34,20 +34,18 @@
#include "llvm/MC/MCAsmInfo.h"
using namespace llvm;
namespace {
cl::opt<bool>
NoFusing("disable-spill-fusing",
cl::desc("Disable fusing of spill code into instructions"));
cl::opt<bool>
PrintFailedFusing("print-failed-fuse-candidates",
cl::desc("Print instructions that the allocator wants to"
" fuse, but the X86 backend currently can't"),
cl::Hidden);
cl::opt<bool>
ReMatPICStubLoad("remat-pic-stub-load",
cl::desc("Re-materialize load from stub in PIC mode"),
cl::init(false), cl::Hidden);
}
static cl::opt<bool>
NoFusing("disable-spill-fusing",
cl::desc("Disable fusing of spill code into instructions"));
static cl::opt<bool>
PrintFailedFusing("print-failed-fuse-candidates",
cl::desc("Print instructions that the allocator wants to"
" fuse, but the X86 backend currently can't"),
cl::Hidden);
static cl::opt<bool>
ReMatPICStubLoad("remat-pic-stub-load",
cl::desc("Re-materialize load from stub in PIC mode"),
cl::init(false), cl::Hidden);
X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
: TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
@ -2215,7 +2213,7 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
// No fusion
if (PrintFailedFusing)
cerr << "We failed to fuse operand " << i << " in " << *MI;
errs() << "We failed to fuse operand " << i << " in " << *MI;
return NULL;
}

10
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -193,11 +193,11 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
#ifndef NDEBUG
DEBUG(errs() << "\nFunction : "
<< MF.getFunction()->getName() << "\n");
DOUT << "<--------->\n";
MI.print(DOUT);
DOUT << "FrameIndex : " << FrameIndex << "\n";
DOUT << "FrameOffset : " << Offset << "\n";
DOUT << "StackSize : " << StackSize << "\n";
DEBUG(errs() << "<--------->\n");
DEBUG(MI.print(errs()));
DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
DEBUG(errs() << "FrameOffset : " << Offset << "\n");
DEBUG(errs() << "StackSize : " << StackSize << "\n");
#endif
Offset += StackSize;