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[PowerPC] Use the MachineCombiner to reassociate fadd/fmul
This is a direct port of the code from the X86 backend (r239486/r240361), which uses the MachineCombiner to reassociate (floating-point) adds/muls to increase ILP, to the PowerPC backend. The rationale is the same. There is a lot of copy-and-paste here between the X86 code and the PowerPC code, and we should extract at least some of this into CodeGen somewhere. However, I don't want to do that until this code is enhanced to handle FMAs as well. After that, we'll be in a better position to extract the common parts. llvm-svn: 242279
This commit is contained in:
Hal Finkel
parent
d668bc2386
commit
db4f85d64e
@ -144,6 +144,9 @@ int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
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UseMI, UseIdx);
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if (!DefMI->getParent())
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return Latency;
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const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
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unsigned Reg = DefMO.getReg();
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@ -186,6 +189,265 @@ int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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return Latency;
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}
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static bool hasVirtualRegDefsInBasicBlock(const MachineInstr &Inst,
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const MachineBasicBlock *MBB) {
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const MachineOperand &Op1 = Inst.getOperand(1);
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const MachineOperand &Op2 = Inst.getOperand(2);
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const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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// We need virtual register definitions.
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MachineInstr *MI1 = nullptr;
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MachineInstr *MI2 = nullptr;
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if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
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MI1 = MRI.getUniqueVRegDef(Op1.getReg());
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if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
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MI2 = MRI.getUniqueVRegDef(Op2.getReg());
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// And they need to be in the trace (otherwise, they won't have a depth).
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if (MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB)
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return true;
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return false;
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}
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static bool hasReassocSibling(const MachineInstr &Inst, bool &Commuted) {
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const MachineBasicBlock *MBB = Inst.getParent();
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const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
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MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
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unsigned AssocOpcode = Inst.getOpcode();
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// If only one operand has the same opcode and it's the second source operand,
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// the operands must be commuted.
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Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
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if (Commuted)
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std::swap(MI1, MI2);
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// 1. The previous instruction must be the same type as Inst.
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// 2. The previous instruction must have virtual register definitions for its
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// operands in the same basic block as Inst.
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// 3. The previous instruction's result must only be used by Inst.
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if (MI1->getOpcode() == AssocOpcode &&
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hasVirtualRegDefsInBasicBlock(*MI1, MBB) &&
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MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg()))
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return true;
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return false;
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}
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// This function does not list all associative and commutative operations, but
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// only those worth feeding through the machine combiner in an attempt to
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// reduce the critical path. Mostly, this means floating-point operations,
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// because they have high latencies (compared to other operations, such and
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// and/or, which are also associative and commutative, but have low latencies).
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//
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// The concept is that these operations can benefit from this kind of
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// transformation:
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//
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// A = ? op ?
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// B = A op X
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// C = B op Y
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// -->
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// A = ? op ?
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// B = X op Y
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// C = A op B
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//
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// breaking the dependency between A and B, allowing them to be executed in
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// parallel (or back-to-back in a pipeline) instead of depending on each other.
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static bool isAssociativeAndCommutative(unsigned Opcode) {
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switch (Opcode) {
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// FP Add:
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case PPC::FADD:
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case PPC::FADDS:
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// FP Multiply:
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case PPC::FMUL:
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case PPC::FMULS:
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// Altivec Add:
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case PPC::VADDFP:
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// VSX Add:
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case PPC::XSADDDP:
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case PPC::XVADDDP:
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case PPC::XVADDSP:
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case PPC::XSADDSP:
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// VSX Multiply:
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case PPC::XSMULDP:
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case PPC::XVMULDP:
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case PPC::XVMULSP:
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case PPC::XSMULSP:
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// QPX Add:
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case PPC::QVFADD:
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case PPC::QVFADDS:
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case PPC::QVFADDSs:
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// QPX Multiply:
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case PPC::QVFMUL:
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case PPC::QVFMULS:
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case PPC::QVFMULSs:
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return true;
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default:
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return false;
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}
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}
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/// Return true if the input instruction is part of a chain of dependent ops
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/// that are suitable for reassociation, otherwise return false.
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/// If the instruction's operands must be commuted to have a previous
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/// instruction of the same type define the first source operand, Commuted will
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/// be set to true.
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static bool isReassocCandidate(const MachineInstr &Inst, bool &Commuted) {
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// 1. The operation must be associative and commutative.
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// 2. The instruction must have virtual register definitions for its
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// operands in the same basic block.
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// 3. The instruction must have a reassociable sibling.
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if (isAssociativeAndCommutative(Inst.getOpcode()) &&
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hasVirtualRegDefsInBasicBlock(Inst, Inst.getParent()) &&
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hasReassocSibling(Inst, Commuted))
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return true;
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return false;
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}
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bool PPCInstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
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// Using the machine combiner in this way is potentially expensive, so
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// restrict to when aggressive optimizations are desired.
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if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
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return false;
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// FP reassociation is only legal when we don't need strict IEEE semantics.
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if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
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return false;
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// Look for this reassociation pattern:
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// B = A op X (Prev)
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// C = B op Y (Root)
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// FIXME: We should also match FMA operations here, where we consider the
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// 'part' of the FMA, either the addition or the multiplication, paired with
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// an actual addition or multiplication.
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bool Commute;
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if (isReassocCandidate(Root, Commute)) {
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// We found a sequence of instructions that may be suitable for a
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// reassociation of operands to increase ILP. Specify each commutation
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// possibility for the Prev instruction in the sequence and let the
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// machine combiner decide if changing the operands is worthwhile.
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if (Commute) {
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Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_YB);
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Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_YB);
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} else {
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Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_BY);
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Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_BY);
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}
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return true;
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}
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return false;
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}
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/// Attempt the following reassociation to reduce critical path length:
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/// B = A op X (Prev)
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/// C = B op Y (Root)
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/// ===>
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/// B = X op Y
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/// C = A op B
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static void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
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MachineCombinerPattern::MC_PATTERN Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
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MachineFunction *MF = Root.getParent()->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
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const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
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// This array encodes the operand index for each parameter because the
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// operands may be commuted. Each row corresponds to a pattern value,
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// and each column specifies the index of A, B, X, Y.
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unsigned OpIdx[4][4] = {
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{ 1, 1, 2, 2 },
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{ 1, 2, 2, 1 },
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{ 2, 1, 1, 2 },
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{ 2, 2, 1, 1 }
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};
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MachineOperand &OpA = Prev.getOperand(OpIdx[Pattern][0]);
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MachineOperand &OpB = Root.getOperand(OpIdx[Pattern][1]);
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MachineOperand &OpX = Prev.getOperand(OpIdx[Pattern][2]);
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MachineOperand &OpY = Root.getOperand(OpIdx[Pattern][3]);
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MachineOperand &OpC = Root.getOperand(0);
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unsigned RegA = OpA.getReg();
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unsigned RegB = OpB.getReg();
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unsigned RegX = OpX.getReg();
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unsigned RegY = OpY.getReg();
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unsigned RegC = OpC.getReg();
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if (TargetRegisterInfo::isVirtualRegister(RegA))
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MRI.constrainRegClass(RegA, RC);
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if (TargetRegisterInfo::isVirtualRegister(RegB))
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MRI.constrainRegClass(RegB, RC);
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if (TargetRegisterInfo::isVirtualRegister(RegX))
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MRI.constrainRegClass(RegX, RC);
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if (TargetRegisterInfo::isVirtualRegister(RegY))
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MRI.constrainRegClass(RegY, RC);
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if (TargetRegisterInfo::isVirtualRegister(RegC))
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MRI.constrainRegClass(RegC, RC);
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// Create a new virtual register for the result of (X op Y) instead of
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// recycling RegB because the MachineCombiner's computation of the critical
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// path requires a new register definition rather than an existing one.
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unsigned NewVR = MRI.createVirtualRegister(RC);
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InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
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unsigned Opcode = Root.getOpcode();
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bool KillA = OpA.isKill();
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bool KillX = OpX.isKill();
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bool KillY = OpY.isKill();
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// Create new instructions for insertion.
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MachineInstrBuilder MIB1 =
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BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
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.addReg(RegX, getKillRegState(KillX))
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.addReg(RegY, getKillRegState(KillY));
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InsInstrs.push_back(MIB1);
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MachineInstrBuilder MIB2 =
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BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
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.addReg(RegA, getKillRegState(KillA))
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.addReg(NewVR, getKillRegState(true));
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InsInstrs.push_back(MIB2);
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// Record old instructions for deletion.
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DelInstrs.push_back(&Prev);
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DelInstrs.push_back(&Root);
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}
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void PPCInstrInfo::genAlternativeCodeSequence(
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MachineInstr &Root,
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MachineCombinerPattern::MC_PATTERN Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
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MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo();
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// Select the previous instruction in the sequence based on the input pattern.
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MachineInstr *Prev = nullptr;
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switch (Pattern) {
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case MachineCombinerPattern::MC_REASSOC_AX_BY:
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case MachineCombinerPattern::MC_REASSOC_XA_BY:
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Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
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break;
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case MachineCombinerPattern::MC_REASSOC_AX_YB:
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case MachineCombinerPattern::MC_REASSOC_XA_YB:
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Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
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}
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assert(Prev && "Unknown pattern for machine combiner");
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reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
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return;
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}
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// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
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bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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@ -63,6 +63,19 @@ enum PPC970_Unit {
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};
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} // end namespace PPCII
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namespace MachineCombinerPattern {
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enum MC_PATTERN : int {
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// These are commutative variants for reassociating a computation chain
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// of the form:
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// B = A op X (Prev)
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// C = B op Y (Root)
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MC_REASSOC_AX_BY = 0,
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MC_REASSOC_AX_YB = 1,
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MC_REASSOC_XA_BY = 2,
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MC_REASSOC_XA_YB = 3,
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};
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} // end namespace MachineCombinerPattern
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class PPCSubtarget;
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class PPCInstrInfo : public PPCGenInstrInfo {
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PPCSubtarget &Subtarget;
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@ -119,6 +132,25 @@ public:
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return false;
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}
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bool useMachineCombiner() const override {
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return true;
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}
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/// Return true when there is potentially a faster code sequence
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/// for an instruction chain ending in <Root>. All potential patterns are
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/// output in the <Pattern> array.
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bool getMachineCombinerPatterns(
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MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &P) const override;
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/// When getMachineCombinerPatterns() finds a pattern, this function generates
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/// the instructions that could replace the original code sequence.
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void genAlternativeCodeSequence(
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MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
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bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const override;
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@ -57,6 +57,11 @@ EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
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cl::desc("Add extra TOC register dependencies"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnableMachineCombinerPass("ppc-machine-combiner",
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cl::desc("Enable the machine combiner pass"),
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cl::init(true), cl::Hidden);
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extern "C" void LLVMInitializePowerPCTarget() {
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// Register the targets
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RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
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@ -316,6 +321,10 @@ bool PPCPassConfig::addPreISel() {
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bool PPCPassConfig::addILPOpts() {
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addPass(&EarlyIfConverterID);
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if (EnableMachineCombinerPass)
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addPass(&MachineCombinerID);
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return true;
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}
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188
test/CodeGen/PowerPC/machine-combiner.ll
Normal file
188
test/CodeGen/PowerPC/machine-combiner.ll
Normal file
@ -0,0 +1,188 @@
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; RUN: llc -O3 -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-PWR
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; RUN: llc -O3 -mcpu=a2q -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-QPX
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Verify that the first two adds are independent regardless of how the inputs are
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; commuted. The destination registers are used as source registers for the third add.
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define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds1:
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; CHECK: # BB#0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd float %x0, %x1
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%t1 = fadd float %t0, %x2
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%t2 = fadd float %t1, %x3
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ret float %t2
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}
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define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds2:
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; CHECK: # BB#0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd float %x0, %x1
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%t1 = fadd float %x2, %t0
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%t2 = fadd float %t1, %x3
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ret float %t2
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}
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define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds3:
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; CHECK: # BB#0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd float %x0, %x1
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%t1 = fadd float %t0, %x2
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%t2 = fadd float %x3, %t1
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ret float %t2
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}
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define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds4:
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; CHECK: # BB#0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd float %x0, %x1
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%t1 = fadd float %x2, %t0
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%t2 = fadd float %x3, %t1
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ret float %t2
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}
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; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not
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; produced because that would cost more compile time.
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define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {
|
||||
; CHECK-LABEL: reassociate_adds5:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK: fadds [[REG12:[0-9]+]], 5, 6
|
||||
; CHECK: fadds [[REG0:[0-9]+]], 1, 2
|
||||
; CHECK: fadds [[REG11:[0-9]+]], 3, 4
|
||||
; CHECK: fadds [[REG13:[0-9]+]], [[REG12]], 7
|
||||
; CHECK: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]
|
||||
; CHECK: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]
|
||||
; CHECK: fadds 1, [[REG2]], 8
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
%t0 = fadd float %x0, %x1
|
||||
%t1 = fadd float %t0, %x2
|
||||
%t2 = fadd float %t1, %x3
|
||||
%t3 = fadd float %t2, %x4
|
||||
%t4 = fadd float %t3, %x5
|
||||
%t5 = fadd float %t4, %x6
|
||||
%t6 = fadd float %t5, %x7
|
||||
ret float %t6
|
||||
}
|
||||
|
||||
; Verify that we reassociate vector instructions too.
|
||||
|
||||
define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
|
||||
; CHECK-LABEL: vector_reassociate_adds1:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2
|
||||
; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4
|
||||
; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]]
|
||||
; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
|
||||
; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
|
||||
; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
%t0 = fadd <4 x float> %x0, %x1
|
||||
%t1 = fadd <4 x float> %t0, %x2
|
||||
%t2 = fadd <4 x float> %t1, %x3
|
||||
ret <4 x float> %t2
|
||||
}
|
||||
|
||||
define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
|
||||
; CHECK-LABEL: vector_reassociate_adds2:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2
|
||||
; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4
|
||||
; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]]
|
||||
; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
|
||||
; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
|
||||
; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
%t0 = fadd <4 x float> %x0, %x1
|
||||
%t1 = fadd <4 x float> %x2, %t0
|
||||
%t2 = fadd <4 x float> %t1, %x3
|
||||
ret <4 x float> %t2
|
||||
}
|
||||
|
||||
define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
|
||||
; CHECK-LABEL: vector_reassociate_adds3:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2
|
||||
; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4
|
||||
; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]]
|
||||
; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
|
||||
; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
|
||||
; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
%t0 = fadd <4 x float> %x0, %x1
|
||||
%t1 = fadd <4 x float> %t0, %x2
|
||||
%t2 = fadd <4 x float> %x3, %t1
|
||||
ret <4 x float> %t2
|
||||
}
|
||||
|
||||
define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
|
||||
; CHECK-LABEL: vector_reassociate_adds4:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2
|
||||
; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4
|
||||
; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]]
|
||||
; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
|
||||
; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
|
||||
; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
|
||||
; CHECK-NEXT: blr
|
||||
|
||||
%t0 = fadd <4 x float> %x0, %x1
|
||||
%t1 = fadd <4 x float> %x2, %t0
|
||||
%t2 = fadd <4 x float> %x3, %t1
|
||||
ret <4 x float> %t2
|
||||
}
|
||||
|
||||
define float @reassociate_adds6(float %x0, float %x1, float %x2, float %x3) {
|
||||
%t0 = fdiv float %x0, %x1
|
||||
%t1 = fadd float %x2, %t0
|
||||
%t2 = fadd float %x3, %t1
|
||||
ret float %t2
|
||||
}
|
||||
|
||||
define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {
|
||||
%t0 = fdiv float %x0, %x1
|
||||
%t1 = fmul float %x2, %t0
|
||||
%t2 = fmul float %x3, %t1
|
||||
ret float %t2
|
||||
}
|
||||
|
||||
define double @reassociate_adds_double(double %x0, double %x1, double %x2, double %x3) {
|
||||
%t0 = fdiv double %x0, %x1
|
||||
%t1 = fadd double %x2, %t0
|
||||
%t2 = fadd double %x3, %t1
|
||||
ret double %t2
|
||||
}
|
||||
|
||||
define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {
|
||||
%t0 = fdiv double %x0, %x1
|
||||
%t1 = fmul double %x2, %t0
|
||||
%t2 = fmul double %x3, %t1
|
||||
ret double %t2
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user