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[PowerPC] Regenerate test
llvm-svn: 353851
This commit is contained in:
Simon Pilgrim
parent
1461178ba9
commit
db8d82f38b
@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: < %s | FileCheck %s
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@ -9,109 +10,121 @@
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; Function Attrs: norecurse nounwind readonly
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define signext i32 @test_pre_inc_disable_1(i8* nocapture readonly %pix1, i32 signext %i_stride_pix1, i8* nocapture readonly %pix2) {
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; CHECK-LABEL: test_pre_inc_disable_1:
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; CHECK: # %bb.0: # %entry
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; CHECK: lfd f0, 0(r5)
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; CHECK: addis r5, r2
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; CHECK: addi r5, r5,
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; CHECK: lxvx v2, 0, r5
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; CHECK: addis r5, r2,
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; CHECK: addi r5, r5,
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; CHECK: lxvx v4, 0, r5
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; CHECK: xxpermdi v5, f0, f0, 2
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; CHECK: xxlxor v3, v3, v3
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; CHECK-DAG: vperm v[[VR1:[0-9]+]], v5, v3, v4
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; CHECK-DAG: vperm v[[VR2:[0-9]+]], v3, v5, v2
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; CHECK-DAG: xvnegsp v[[VR3:[0-9]+]], v[[VR1]]
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; CHECK-DAG: xvnegsp v[[VR4:[0-9]+]], v[[VR2]]
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; CHECK: .LBB0_1: # %for.cond1.preheader
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; CHECK: lfd f0, 0(r3)
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; CHECK: xxpermdi v1, f0, f0, 2
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; CHECK: vperm v6, v3, v1, v2
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; CHECK: vperm v1, v1, v3, v4
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; CHECK-DAG: xvnegsp v6, v6
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; CHECK-DAG: xvnegsp v1, v1
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; CHECK-DAG: vabsduw v1, v1, v[[VR3]]
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; CHECK-DAG: vabsduw v6, v6, v[[VR4]]
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; CHECK: vadduwm v1, v1, v6
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; CHECK: xxswapd v6, v1
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; CHECK: vadduwm v1, v1, v6
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; CHECK: xxspltw v6, v1, 2
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; CHECK: vadduwm v1, v1, v6
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; CHECK: vextuwrx r7, r5, v1
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; CHECK: ldux r8, r3, r4
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; CHECK: add r3, r3, r4
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; CHECK: add r6, r7, r6
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; CHECK: mtvsrd f0, r8
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; CHECK: xxswapd v1, vs0
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; CHECK: vperm v6, v3, v1, v2
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; CHECK: vperm v1, v1, v3, v4
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; CHECK-DAG: xvnegsp v6, v6
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; CHECK-DAG: xvnegsp v1, v1
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; CHECK-DAG: vabsduw v1, v1, v[[VR3]]
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; CHECK-DAG: vabsduw v6, v6, v[[VR4]]
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; CHECK: vadduwm v1, v1, v6
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; CHECK: xxswapd v6, v1
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; CHECK: vadduwm v1, v1, v6
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; CHECK: xxspltw v6, v1, 2
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; CHECK: vadduwm v1, v1, v6
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; CHECK: vextuwrx r7, r5, v1
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; CHECK: add r6, r7, r6
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; CHECK: bdnz .LBB0_1
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; CHECK: extsw r3, r6
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; CHECK: blr
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lfd f0, 0(r5)
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; CHECK-NEXT: addis r5, r2, .LCPI0_0@toc@ha
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; CHECK-NEXT: addi r5, r5, .LCPI0_0@toc@l
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; CHECK-NEXT: lxvx v2, 0, r5
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; CHECK-NEXT: addis r5, r2, .LCPI0_1@toc@ha
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; CHECK-NEXT: addi r5, r5, .LCPI0_1@toc@l
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; CHECK-NEXT: lxvx v4, 0, r5
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; CHECK-NEXT: xxpermdi v5, f0, f0, 2
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; CHECK-NEXT: xxlxor v3, v3, v3
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; CHECK-NEXT: li r5, 4
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; CHECK-NEXT: vperm v0, v3, v5, v2
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; CHECK-NEXT: mtctr r5
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; CHECK-NEXT: li r5, 0
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; CHECK-NEXT: vperm v1, v5, v3, v4
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; CHECK-NEXT: li r6, 0
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; CHECK-NEXT: xvnegsp v5, v0
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; CHECK-NEXT: xvnegsp v0, v1
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lfd f0, 0(r3)
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; CHECK-NEXT: xxpermdi v1, f0, f0, 2
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; CHECK-NEXT: vperm v6, v3, v1, v2
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; CHECK-NEXT: vperm v1, v1, v3, v4
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; CHECK-NEXT: xvnegsp v6, v6
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; CHECK-NEXT: xvnegsp v1, v1
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; CHECK-NEXT: vabsduw v6, v6, v5
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; CHECK-NEXT: vabsduw v1, v1, v0
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; CHECK-NEXT: vadduwm v1, v1, v6
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; CHECK-NEXT: xxswapd v6, v1
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; CHECK-NEXT: vadduwm v1, v1, v6
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; CHECK-NEXT: xxspltw v6, v1, 2
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; CHECK-NEXT: vadduwm v1, v1, v6
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; CHECK-NEXT: vextuwrx r7, r5, v1
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; CHECK-NEXT: ldux r8, r3, r4
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; CHECK-NEXT: add r3, r3, r4
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; CHECK-NEXT: add r6, r7, r6
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; CHECK-NEXT: mtvsrd f0, r8
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; CHECK-NEXT: xxswapd v1, vs0
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; CHECK-NEXT: vperm v6, v3, v1, v2
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; CHECK-NEXT: vperm v1, v1, v3, v4
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; CHECK-NEXT: xvnegsp v6, v6
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; CHECK-NEXT: xvnegsp v1, v1
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; CHECK-NEXT: vabsduw v6, v6, v5
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; CHECK-NEXT: vabsduw v1, v1, v0
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; CHECK-NEXT: vadduwm v1, v1, v6
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; CHECK-NEXT: xxswapd v6, v1
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; CHECK-NEXT: vadduwm v1, v1, v6
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; CHECK-NEXT: xxspltw v6, v1, 2
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; CHECK-NEXT: vadduwm v1, v1, v6
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; CHECK-NEXT: vextuwrx r7, r5, v1
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; CHECK-NEXT: add r6, r7, r6
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; CHECK-NEXT: bdnz .LBB0_1
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; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
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; CHECK-NEXT: extsw r3, r6
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; CHECK-NEXT: blr
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;
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; P9BE-LABEL: test_pre_inc_disable_1:
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; P9BE: lfd f0, 0(r5)
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; P9BE: addis r5, r2,
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; P9BE: addi r5, r5,
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; P9BE: lxvx v2, 0, r5
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; P9BE: addis r5, r2,
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; P9BE: addi r5, r5,
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; P9BE: lxvx v4, 0, r5
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; P9BE: xxlor v5, vs0, vs0
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; P9BE: xxlxor v3, v3, v3
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; P9BE-DAG: li r5, 0
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; P9BE-DAG: vperm v[[VR1:[0-9]+]], v3, v5, v2
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; P9BE-DAG: vperm v[[VR2:[0-9]+]], v3, v5, v4
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; P9BE-DAG: xvnegsp v[[VR3:[0-9]+]], v[[VR1]]
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; P9BE-DAG: xvnegsp v[[VR4:[0-9]+]], v[[VR2]]
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; P9BE: .LBB0_1: # %for.cond1.preheader
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; P9BE: lfd f0, 0(r3)
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; P9BE: xxlor v1, vs0, vs0
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; P9BE: vperm v6, v3, v1, v4
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; P9BE: vperm v1, v3, v1, v2
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; P9BE-DAG: xvnegsp v6, v6
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; P9BE-DAG: xvnegsp v1, v1
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; P9BE-DAG: vabsduw v1, v1, v[[VR3]]
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; P9BE-DAG: vabsduw v6, v6, v[[VR4]]
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; P9BE: vadduwm v1, v6, v1
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; P9BE: xxswapd v6, v1
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; P9BE: vadduwm v1, v1, v6
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; P9BE: xxspltw v6, v1, 1
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; P9BE: vadduwm v1, v1, v6
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; P9BE: vextuwlx r[[GR1:[0-9]+]], r5, v1
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; P9BE: add r6, r[[GR1]], r6
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; P9BE: ldux r[[GR2:[0-9]+]], r3, r4
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; P9BE: add r3, r3, r4
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; P9BE: mtvsrd v1, r[[GR2]]
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; P9BE: vperm v6, v3, v1, v2
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; P9BE: vperm v1, v3, v1, v4
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; P9BE-DAG: xvnegsp v6, v6
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; P9BE-DAG: xvnegsp v1, v1
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; P9BE-DAG: vabsduw v1, v1, v[[VR4]]
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; P9BE-DAG: vabsduw v6, v6, v[[VR3]]
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; P9BE: vadduwm v1, v1, v6
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; P9BE: xxswapd v6, v1
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; P9BE: vadduwm v1, v1, v6
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; P9BE: xxspltw v6, v1, 1
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; P9BE: vadduwm v1, v1, v6
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; P9BE: vextuwlx r7, r5, v1
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; P9BE: add r6, r7, r6
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; P9BE: bdnz .LBB0_1
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; P9BE: extsw r3, r6
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; P9BE: blr
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 0(r5)
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; P9BE-NEXT: addis r5, r2, .LCPI0_0@toc@ha
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; P9BE-NEXT: addi r5, r5, .LCPI0_0@toc@l
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; P9BE-NEXT: lxvx v2, 0, r5
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; P9BE-NEXT: addis r5, r2, .LCPI0_1@toc@ha
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; P9BE-NEXT: addi r5, r5, .LCPI0_1@toc@l
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; P9BE-NEXT: lxvx v4, 0, r5
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; P9BE-NEXT: li r5, 4
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; P9BE-NEXT: xxlor v5, vs0, vs0
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; P9BE-NEXT: xxlxor v3, v3, v3
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; P9BE-NEXT: vperm v0, v3, v5, v2
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; P9BE-NEXT: mtctr r5
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; P9BE-NEXT: li r5, 0
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; P9BE-NEXT: vperm v1, v3, v5, v4
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; P9BE-NEXT: li r6, 0
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; P9BE-NEXT: xvnegsp v5, v0
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; P9BE-NEXT: xvnegsp v0, v1
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; P9BE-NEXT: .p2align 4
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; P9BE-NEXT: .LBB0_1: # %for.cond1.preheader
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; P9BE-NEXT: # =>This Inner Loop Header: Depth=1
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; P9BE-NEXT: lfd f0, 0(r3)
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; P9BE-NEXT: xxlor v1, vs0, vs0
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; P9BE-NEXT: vperm v6, v3, v1, v4
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; P9BE-NEXT: vperm v1, v3, v1, v2
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; P9BE-NEXT: xvnegsp v1, v1
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; P9BE-NEXT: xvnegsp v6, v6
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; P9BE-NEXT: vabsduw v1, v1, v5
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; P9BE-NEXT: vabsduw v6, v6, v0
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; P9BE-NEXT: vadduwm v1, v6, v1
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; P9BE-NEXT: xxswapd v6, v1
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; P9BE-NEXT: vadduwm v1, v1, v6
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; P9BE-NEXT: xxspltw v6, v1, 1
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; P9BE-NEXT: vadduwm v1, v1, v6
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; P9BE-NEXT: vextuwlx r7, r5, v1
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; P9BE-NEXT: add r6, r7, r6
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; P9BE-NEXT: ldux r7, r3, r4
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; P9BE-NEXT: add r3, r3, r4
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; P9BE-NEXT: mtvsrd v1, r7
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; P9BE-NEXT: vperm v6, v3, v1, v2
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; P9BE-NEXT: vperm v1, v3, v1, v4
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; P9BE-NEXT: xvnegsp v6, v6
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; P9BE-NEXT: xvnegsp v1, v1
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; P9BE-NEXT: vabsduw v6, v6, v5
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; P9BE-NEXT: vabsduw v1, v1, v0
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; P9BE-NEXT: vadduwm v1, v1, v6
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; P9BE-NEXT: xxswapd v6, v1
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; P9BE-NEXT: vadduwm v1, v1, v6
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; P9BE-NEXT: xxspltw v6, v1, 1
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; P9BE-NEXT: vadduwm v1, v1, v6
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; P9BE-NEXT: vextuwlx r7, r5, v1
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; P9BE-NEXT: add r6, r7, r6
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; P9BE-NEXT: bdnz .LBB0_1
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; P9BE-NEXT: # %bb.2: # %for.cond.cleanup
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; P9BE-NEXT: extsw r3, r6
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; P9BE-NEXT: blr
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entry:
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%idx.ext = sext i32 %i_stride_pix1 to i64
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%0 = bitcast i8* %pix2 to <8 x i8>*
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@ -166,58 +179,62 @@ for.cond.cleanup: ; preds = %for.cond1.preheader
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; Function Attrs: norecurse nounwind readonly
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define signext i32 @test_pre_inc_disable_2(i8* nocapture readonly %pix1, i8* nocapture readonly %pix2) {
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; CHECK-LABEL: test_pre_inc_disable_2:
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; CHECK: lfd f0, 0(r3)
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; CHECK: addis r3, r2,
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; CHECK: addi r3, r3, .LCPI1_0@toc@l
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; CHECK: lxvx v4, 0, r3
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; CHECK: addis r3, r2,
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; CHECK: xxpermdi v2, f0, f0, 2
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; CHECK: lfd f0, 0(r4)
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; CHECK: addi r3, r3, .LCPI1_1@toc@l
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; CHECK: xxlxor v3, v3, v3
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; CHECK: lxvx v0, 0, r3
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; CHECK: xxpermdi v1, f0, f0, 2
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; CHECK: vperm v5, v2, v3, v4
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; CHECK: vperm v2, v3, v2, v0
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; CHECK: vperm v0, v3, v1, v0
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; CHECK: vperm v3, v1, v3, v4
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; CHECK: vabsduw v2, v2, v0
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; CHECK: vabsduw v3, v5, v3
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; CHECK: vadduwm v2, v3, v2
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; CHECK: xxswapd v3, v2
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; CHECK: vadduwm v2, v2, v3
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; CHECK: xxspltw v3, v2, 2
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; CHECK: vadduwm v2, v2, v3
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; CHECK: vextuwrx r3, r3, v2
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; CHECK: extsw r3, r3
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; CHECK: blr
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lfd f0, 0(r3)
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; CHECK-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; CHECK-NEXT: lxvx v4, 0, r3
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; CHECK-NEXT: addis r3, r2, .LCPI1_1@toc@ha
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; CHECK-NEXT: xxpermdi v2, f0, f0, 2
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; CHECK-NEXT: lfd f0, 0(r4)
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; CHECK-NEXT: addi r3, r3, .LCPI1_1@toc@l
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; CHECK-NEXT: xxlxor v3, v3, v3
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; CHECK-NEXT: lxvx v0, 0, r3
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; CHECK-NEXT: xxpermdi v1, f0, f0, 2
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; CHECK-NEXT: vperm v5, v2, v3, v4
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; CHECK-NEXT: vperm v2, v3, v2, v0
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; CHECK-NEXT: vperm v0, v3, v1, v0
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; CHECK-NEXT: vperm v3, v1, v3, v4
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; CHECK-NEXT: vabsduw v2, v2, v0
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; CHECK-NEXT: vabsduw v3, v5, v3
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; CHECK-NEXT: vadduwm v2, v3, v2
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; CHECK-NEXT: xxswapd v3, v2
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; CHECK-NEXT: li r3, 0
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; CHECK-NEXT: vadduwm v2, v2, v3
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; CHECK-NEXT: xxspltw v3, v2, 2
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; CHECK-NEXT: vadduwm v2, v2, v3
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; CHECK-NEXT: vextuwrx r3, r3, v2
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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;
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; P9BE-LABEL: test_pre_inc_disable_2:
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; P9BE: lfd f0, 0(r3)
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; P9BE: addis r3, r2,
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; P9BE: addi r3, r3,
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; P9BE: lxvx v4, 0, r3
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; P9BE: addis r3, r2,
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; P9BE: addi r3, r3,
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; P9BE: xxlor v2, vs0, vs0
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; P9BE: lfd f0, 0(r4)
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; P9BE: lxvx v0, 0, r3
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; P9BE: xxlxor v3, v3, v3
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; P9BE: xxlor v1, vs0, vs0
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; P9BE: vperm v5, v3, v2, v4
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; P9BE: vperm v2, v3, v2, v0
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; P9BE: vperm v0, v3, v1, v0
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; P9BE: vperm v3, v3, v1, v4
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; P9BE: vabsduw v2, v2, v0
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; P9BE: vabsduw v3, v5, v3
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; P9BE: vadduwm v2, v3, v2
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; P9BE: xxswapd v3, v2
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; P9BE: vadduwm v2, v2, v3
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; P9BE: xxspltw v3, v2, 1
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; P9BE: vadduwm v2, v2, v3
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; P9BE: vextuwlx r3, r3, v2
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; P9BE: extsw r3, r3
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; P9BE: blr
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; P9BE: # %bb.0: # %entry
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; P9BE-NEXT: lfd f0, 0(r3)
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; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; P9BE-NEXT: lxvx v4, 0, r3
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; P9BE-NEXT: addis r3, r2, .LCPI1_1@toc@ha
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; P9BE-NEXT: addi r3, r3, .LCPI1_1@toc@l
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; P9BE-NEXT: xxlor v2, vs0, vs0
|
||||
; P9BE-NEXT: lfd f0, 0(r4)
|
||||
; P9BE-NEXT: lxvx v0, 0, r3
|
||||
; P9BE-NEXT: xxlxor v3, v3, v3
|
||||
; P9BE-NEXT: xxlor v1, vs0, vs0
|
||||
; P9BE-NEXT: vperm v5, v3, v2, v4
|
||||
; P9BE-NEXT: vperm v2, v3, v2, v0
|
||||
; P9BE-NEXT: vperm v0, v3, v1, v0
|
||||
; P9BE-NEXT: vperm v3, v3, v1, v4
|
||||
; P9BE-NEXT: vabsduw v2, v2, v0
|
||||
; P9BE-NEXT: vabsduw v3, v5, v3
|
||||
; P9BE-NEXT: vadduwm v2, v3, v2
|
||||
; P9BE-NEXT: xxswapd v3, v2
|
||||
; P9BE-NEXT: vadduwm v2, v2, v3
|
||||
; P9BE-NEXT: xxspltw v3, v2, 1
|
||||
; P9BE-NEXT: vadduwm v2, v2, v3
|
||||
; P9BE-NEXT: li r3, 0
|
||||
; P9BE-NEXT: vextuwlx r3, r3, v2
|
||||
; P9BE-NEXT: extsw r3, r3
|
||||
; P9BE-NEXT: blr
|
||||
entry:
|
||||
%0 = bitcast i8* %pix1 to <8 x i8>*
|
||||
%1 = load <8 x i8>, <8 x i8>* %0, align 1
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user