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[AMDGPU] Fix s_branch with -1 offset
Summary: In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0. ''' label: s_branch label // should emit [0xff,0xff,0x82,0xbf] ''' Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result. Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl Differential Revision: https://reviews.llvm.org/D24671 llvm-svn: 281896
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@ -133,24 +133,21 @@ void AMDGPUAsmBackend::processFixupValue(const MCAssembler &Asm,
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const MCValue &Target, uint64_t &Value,
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bool &IsResolved) {
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if (IsResolved)
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(void)adjustFixupValue(Fixup, Value, &Asm.getContext());
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Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
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}
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void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value,
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bool IsPCRel) const {
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unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
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if (!Value)
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return; // Doesn't change encoding.
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Value = adjustFixupValue(Fixup, Value, nullptr);
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MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
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uint32_t Offset = Fixup.getOffset();
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assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
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@ -1,17 +1,24 @@
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// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
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// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -filetype=obj %s | llvm-objdump -disassemble -mcpu=fiji - | FileCheck %s --check-prefix=BIN
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loop_start:
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s_branch loop_start
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// VI: s_branch loop_start ; encoding: [A,A,0x82,0xbf]
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// VI-NEXT: ; fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
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// BIN: loop_start:
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// BIN-NEXT: BF82FFFF
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s_branch loop_end
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// VI: s_branch loop_end ; encoding: [A,A,0x82,0xbf]
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// VI-NEXT: ; fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
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// BIN: BF820000
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// BIN: loop_end:
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loop_end:
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s_branch gds
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// VI: s_branch gds ; encoding: [A,A,0x82,0xbf]
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// VI-NEXT: ; fixup A - offset: 0, value: gds, kind: fixup_si_sopp_br
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// BIN: BF820000
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// BIN: gds:
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gds:
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s_nop 0
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