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[bpf] add support for bswap instructions
BPF has cpu_to_be and cpu_to_le instructions. For now assume little endian and generate cpu_to_be for ISD::BSWAP. llvm-svn: 233620
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@ -137,7 +137,6 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
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setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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setOperationAction(ISD::CTTZ, MVT::i64, Custom);
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setOperationAction(ISD::CTTZ, MVT::i64, Custom);
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setOperationAction(ISD::CTLZ, MVT::i64, Custom);
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setOperationAction(ISD::CTLZ, MVT::i64, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
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@ -484,6 +484,33 @@ def XADD64 : XADD<3, "xadd64", atomic_load_add_64>;
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// undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
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// undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
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}
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}
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// bswap16, bswap32, bswap64
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class BSWAP<bits<32> SizeOp, string OpcodeStr, list<dag> Pattern>
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: InstBPF<(outs GPR:$dst), (ins GPR:$src),
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!strconcat(OpcodeStr, "\t$dst"),
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Pattern> {
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bits<4> op;
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bits<1> BPFSrc;
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bits<4> dst;
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bits<32> imm;
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let Inst{63-60} = op;
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let Inst{59} = BPFSrc;
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let Inst{51-48} = dst;
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let Inst{31-0} = imm;
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let op = 0xd; // BPF_END
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let BPFSrc = 1; // BPF_TO_BE (TODO: use BPF_TO_LE for big-endian target)
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let BPFClass = 4; // BPF_ALU
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let imm = SizeOp;
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}
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let Constraints = "$dst = $src" in {
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def BSWAP16 : BSWAP<16, "bswap16", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
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def BSWAP32 : BSWAP<32, "bswap32", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
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def BSWAP64 : BSWAP<64, "bswap64", [(set GPR:$dst, (bswap GPR:$src))]>;
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}
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let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
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let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
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hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
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hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
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class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
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class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
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@ -61,3 +61,28 @@ entry:
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declare void @bar(i64, i32) #1
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declare void @bar(i64, i32) #1
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declare i64 @llvm.bpf.pseudo(i64, i64) #2
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declare i64 @llvm.bpf.pseudo(i64, i64) #2
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define i32 @bswap(i64 %a, i64 %b, i64 %c) #0 {
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entry:
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%0 = tail call i64 @llvm.bswap.i64(i64 %a)
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%conv = trunc i64 %b to i32
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%1 = tail call i32 @llvm.bswap.i32(i32 %conv)
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%conv1 = zext i32 %1 to i64
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%add = add i64 %conv1, %0
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%conv2 = trunc i64 %c to i16
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%2 = tail call i16 @llvm.bswap.i16(i16 %conv2)
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%conv3 = zext i16 %2 to i64
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%add4 = add i64 %add, %conv3
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%conv5 = trunc i64 %add4 to i32
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ret i32 %conv5
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; CHECK-LABEL: bswap:
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; CHECK: bswap64 r1 # encoding: [0xdc,0x01,0x00,0x00,0x40,0x00,0x00,0x00]
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; CHECK: bswap32 r2 # encoding: [0xdc,0x02,0x00,0x00,0x20,0x00,0x00,0x00]
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; CHECK: add r2, r1 # encoding: [0x0f,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
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; CHECK: bswap16 r3 # encoding: [0xdc,0x03,0x00,0x00,0x10,0x00,0x00,0x00]
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; CHECK: add r2, r3 # encoding: [0x0f,0x32,0x00,0x00,0x00,0x00,0x00,0x00]
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}
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declare i64 @llvm.bswap.i64(i64) #1
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declare i32 @llvm.bswap.i32(i32) #1
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declare i16 @llvm.bswap.i16(i16) #1
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