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AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and VBROADCASTF32x2 instructions.
Differential Revision: http://reviews.llvm.org/D14216 llvm-svn: 251781
This commit is contained in:
Igor Breger
parent
0354af2e80
commit
dd070c17bb
@ -4886,6 +4886,31 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v8i64_ty],
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Intrinsic<[llvm_v8i64_ty],
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[llvm_v2i64_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
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[llvm_v2i64_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_broadcastf32x2_256 :
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GCCBuiltin<"__builtin_ia32_broadcastf32x2_256_mask">,
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Intrinsic<[llvm_v8f32_ty],
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[llvm_v4f32_ty, llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_broadcastf32x2_512 :
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GCCBuiltin<"__builtin_ia32_broadcastf32x2_512_mask">,
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Intrinsic<[llvm_v16f32_ty],
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[llvm_v4f32_ty, llvm_v16f32_ty, llvm_i16_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_broadcasti32x2_128 :
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GCCBuiltin<"__builtin_ia32_broadcasti32x2_128_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_broadcasti32x2_256 :
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GCCBuiltin<"__builtin_ia32_broadcasti32x2_256_mask">,
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v4i32_ty, llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_broadcasti32x2_512 :
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GCCBuiltin<"__builtin_ia32_broadcasti32x2_512_mask">,
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Intrinsic<[llvm_v16i32_ty],
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[llvm_v4i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
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def int_x86_avx512_pbroadcastd_i32_512 :
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def int_x86_avx512_pbroadcastd_i32_512 :
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Intrinsic<[llvm_v16i32_ty], [llvm_i32_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v16i32_ty], [llvm_i32_ty], [IntrNoMem]>;
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@ -1047,6 +1047,46 @@ defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
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EVEX_V512, EVEX_CD8<32, CD8VT8>;
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EVEX_V512, EVEX_CD8<32, CD8VT8>;
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}
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}
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multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
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X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
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SDNode OpNode = X86SubVBroadcast> {
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defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
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(ins _Src.RC:$src), OpcodeStr, "$src", "$src",
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(_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
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T8PD, EVEX;
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let mayLoad = 1 in
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defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
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(ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
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(_Dst.VT (OpNode
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(_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
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T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
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}
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multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _> {
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let Predicates = [HasDQI] in
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defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
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EVEX_V512;
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let Predicates = [HasDQI, HasVLX] in
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defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
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EVEX_V256;
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}
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multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _> :
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avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
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let Predicates = [HasDQI, HasVLX] in
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defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
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X86SubV32x2Broadcast>, EVEX_V128;
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}
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defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
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avx512vl_i32_info>;
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defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
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avx512vl_f32_info>;
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def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
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def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
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(VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
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(VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
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def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
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def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
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@ -382,6 +382,10 @@ def X86Vfpclasss : SDNode<"X86ISD::VFPCLASS", SDTypeProfile<1, 2, [SDTCisInt<0
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def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
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def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisSubVecOfVec<1, 0>]>, []>;
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SDTCisSubVecOfVec<1, 0>]>, []>;
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// SDTCisSubVecOfVec restriction cannot be applied for 128 bit version of VBROADCASTI32x2.
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def X86SubV32x2Broadcast : SDNode<"X86ISD::SUBV_BROADCAST",
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SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>, []>;
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def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
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def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
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def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
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def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
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[SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
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@ -420,6 +420,16 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_mask_blend_w_128, BLEND, X86ISD::SELECT, 0),
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X86_INTRINSIC_DATA(avx512_mask_blend_w_128, BLEND, X86ISD::SELECT, 0),
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X86_INTRINSIC_DATA(avx512_mask_blend_w_256, BLEND, X86ISD::SELECT, 0),
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X86_INTRINSIC_DATA(avx512_mask_blend_w_256, BLEND, X86ISD::SELECT, 0),
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X86_INTRINSIC_DATA(avx512_mask_blend_w_512, BLEND, X86ISD::SELECT, 0),
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X86_INTRINSIC_DATA(avx512_mask_blend_w_512, BLEND, X86ISD::SELECT, 0),
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X86_INTRINSIC_DATA(avx512_mask_broadcastf32x2_256, INTR_TYPE_1OP_MASK,
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X86ISD::SUBV_BROADCAST, 0),
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X86_INTRINSIC_DATA(avx512_mask_broadcastf32x2_512, INTR_TYPE_1OP_MASK,
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X86ISD::SUBV_BROADCAST, 0),
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X86_INTRINSIC_DATA(avx512_mask_broadcasti32x2_128, INTR_TYPE_1OP_MASK,
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X86ISD::SUBV_BROADCAST, 0),
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X86_INTRINSIC_DATA(avx512_mask_broadcasti32x2_256, INTR_TYPE_1OP_MASK,
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X86ISD::SUBV_BROADCAST, 0),
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X86_INTRINSIC_DATA(avx512_mask_broadcasti32x2_512, INTR_TYPE_1OP_MASK,
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X86ISD::SUBV_BROADCAST, 0),
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X86_INTRINSIC_DATA(avx512_mask_cmp_b_128, CMP_MASK_CC, X86ISD::CMPM, 0),
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X86_INTRINSIC_DATA(avx512_mask_cmp_b_128, CMP_MASK_CC, X86ISD::CMPM, 0),
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X86_INTRINSIC_DATA(avx512_mask_cmp_b_256, CMP_MASK_CC, X86ISD::CMPM, 0),
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X86_INTRINSIC_DATA(avx512_mask_cmp_b_256, CMP_MASK_CC, X86ISD::CMPM, 0),
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X86_INTRINSIC_DATA(avx512_mask_cmp_b_512, CMP_MASK_CC, X86ISD::CMPM, 0),
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X86_INTRINSIC_DATA(avx512_mask_cmp_b_512, CMP_MASK_CC, X86ISD::CMPM, 0),
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@ -501,3 +501,43 @@ define i8 @test_int_x86_avx512_mask_fpclass_ss(<4 x float> %x0, i8 %x1) {
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%res2 = add i8 %res, %res1
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%res2 = add i8 %res, %res1
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ret i8 %res2
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ret i8 %res2
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}
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}
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declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float>, <16 x float>, i16)
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define <16 x float>@test_int_x86_avx512_mask_broadcastf32x2_512(<4 x float> %x0, <16 x float> %x2, i16 %x3) {
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; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x2_512:
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; CHECK: ## BB#0:
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vbroadcastf32x2 %xmm0, %zmm1 {%k1}
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; CHECK-NEXT: vbroadcastf32x2 %xmm0, %zmm2 {%k1} {z}
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; CHECK-NEXT: vbroadcastf32x2 %xmm0, %zmm0
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; CHECK-NEXT: vaddps %zmm2, %zmm1, %zmm1
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; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
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; CHECK-NEXT: retq
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%res = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float> %x0, <16 x float> %x2, i16 %x3)
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%res1 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float> %x0, <16 x float> zeroinitializer, i16 %x3)
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%res2 = call <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float> %x0, <16 x float> %x2, i16 -1)
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%res3 = fadd <16 x float> %res, %res1
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%res4 = fadd <16 x float> %res3, %res2
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ret <16 x float> %res4
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}
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declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x2.512(<4 x i32>, <16 x i32>, i16)
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define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x2_512(<4 x i32> %x0, <16 x i32> %x2, i16 %x3) {
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; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_512:
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; CHECK: ## BB#0:
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; CHECK-NEXT: kmovw %edi, %k1
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; CHECK-NEXT: vbroadcasti32x2 %xmm0, %zmm1 {%k1}
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; CHECK-NEXT: vbroadcasti32x2 %xmm0, %zmm2 {%k1} {z}
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; CHECK-NEXT: vbroadcasti32x2 %xmm0, %zmm0
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; CHECK-NEXT: vpaddd %zmm2, %zmm1, %zmm1
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; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
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; CHECK-NEXT: retq
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%res = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x2.512(<4 x i32> %x0, <16 x i32> %x2, i16 %x3)
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%res1 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x2.512(<4 x i32> %x0, <16 x i32> zeroinitializer, i16 %x3)
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%res2 = call <16 x i32> @llvm.x86.avx512.mask.broadcasti32x2.512(<4 x i32> %x0, <16 x i32> %x2, i16 -1)
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%res3 = add <16 x i32> %res, %res1
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%res4 = add <16 x i32> %res3, %res2
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ret <16 x i32> %res4
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}
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@ -1772,3 +1772,64 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_256(<4 x double> %x0, i8 %x1) {
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%res2 = add i8 %res, %res1
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%res2 = add i8 %res, %res1
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ret i8 %res2
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ret i8 %res2
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}
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}
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declare <8 x float> @llvm.x86.avx512.mask.broadcastf32x2.256(<4 x float>, <8 x float>, i8)
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define <8 x float>@test_int_x86_avx512_mask_broadcastf32x2_256(<4 x float> %x0, <8 x float> %x2, i8 %x3) {
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; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x2_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: kmovb %edi, %k1
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; CHECK-NEXT: vbroadcastf32x2 %xmm0, %ymm1 {%k1}
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; CHECK-NEXT: vbroadcastf32x2 %xmm0, %ymm2 {%k1} {z}
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; CHECK-NEXT: vbroadcastf32x2 %xmm0, %ymm0
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; CHECK-NEXT: vaddps %ymm2, %ymm1, %ymm1
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; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%res = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x2.256(<4 x float> %x0, <8 x float> %x2, i8 %x3)
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%res1 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x2.256(<4 x float> %x0, <8 x float> zeroinitializer, i8 %x3)
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%res2 = call <8 x float> @llvm.x86.avx512.mask.broadcastf32x2.256(<4 x float> %x0, <8 x float> %x2, i8 -1)
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%res3 = fadd <8 x float> %res, %res1
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%res4 = fadd <8 x float> %res3, %res2
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ret <8 x float> %res4
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}
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declare <8 x i32> @llvm.x86.avx512.mask.broadcasti32x2.256(<4 x i32>, <8 x i32>, i8)
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define <8 x i32>@test_int_x86_avx512_mask_broadcasti32x2_256(<4 x i32> %x0, <8 x i32> %x2, i8 %x3) {
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; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_256:
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; CHECK: ## BB#0:
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; CHECK-NEXT: kmovb %edi, %k1
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; CHECK-NEXT: vbroadcasti32x2 %xmm0, %ymm1 {%k1}
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; CHECK-NEXT: vbroadcasti32x2 %xmm0, %ymm2 {%k1} {z}
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; CHECK-NEXT: vbroadcasti32x2 %xmm0, %ymm0
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; CHECK-NEXT: vpaddd %ymm2, %ymm1, %ymm1
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; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%res = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x2.256(<4 x i32> %x0, <8 x i32> %x2, i8 %x3)
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%res1 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x2.256(<4 x i32> %x0, <8 x i32> zeroinitializer, i8 %x3)
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%res2 = call <8 x i32> @llvm.x86.avx512.mask.broadcasti32x2.256(<4 x i32> %x0, <8 x i32> %x2, i8 -1)
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%res3 = add <8 x i32> %res, %res1
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%res4 = add <8 x i32> %res3, %res2
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ret <8 x i32> %res4
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}
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declare <4 x i32> @llvm.x86.avx512.mask.broadcasti32x2.128(<4 x i32>, <4 x i32>, i8)
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define <4 x i32>@test_int_x86_avx512_mask_broadcasti32x2_128(<4 x i32> %x0, <4 x i32> %x2, i8 %x3) {
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; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_128:
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; CHECK: ## BB#0:
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; CHECK-NEXT: kmovb %edi, %k1
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; CHECK-NEXT: vbroadcasti32x2 %xmm0, %xmm1 {%k1}
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; CHECK-NEXT: vbroadcasti32x2 %xmm0, %xmm2 {%k1} {z}
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; CHECK-NEXT: vbroadcasti32x2 %xmm0, %xmm0
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; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1
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; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; CHECK-NEXT: retq
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%res = call <4 x i32> @llvm.x86.avx512.mask.broadcasti32x2.128(<4 x i32> %x0, <4 x i32> %x2, i8 %x3)
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%res1 = call <4 x i32> @llvm.x86.avx512.mask.broadcasti32x2.128(<4 x i32> %x0, <4 x i32> zeroinitializer, i8 %x3)
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%res2 = call <4 x i32> @llvm.x86.avx512.mask.broadcasti32x2.128(<4 x i32> %x0, <4 x i32> %x2, i8 -1)
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%res3 = add <4 x i32> %res, %res1
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%res4 = add <4 x i32> %res3, %res2
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ret <4 x i32> %res4
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}
|
||||||
|
|
||||||
|
|||||||
@ -3991,3 +3991,148 @@
|
|||||||
// CHECK: vfpclassss $123, -516(%rdx), %k4
|
// CHECK: vfpclassss $123, -516(%rdx), %k4
|
||||||
// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
|
// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x67,0xa2,0xfc,0xfd,0xff,0xff,0x7b]
|
||||||
vfpclassss $0x7b,-516(%rdx), %k4
|
vfpclassss $0x7b,-516(%rdx), %k4
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm31, %zmm30
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x48,0x59,0xf7]
|
||||||
|
vbroadcasti32x2 %xmm31, %zmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm31, %zmm30 {%k5}
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x4d,0x59,0xf7]
|
||||||
|
vbroadcasti32x2 %xmm31, %zmm30 {%k5}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm31, %zmm30 {%k5} {z}
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0xcd,0x59,0xf7]
|
||||||
|
vbroadcasti32x2 %xmm31, %zmm30 {%k5} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 (%rcx), %zmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x59,0x31]
|
||||||
|
vbroadcasti32x2 (%rcx), %zmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 291(%rax,%r14,8), %zmm30
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x48,0x59,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||||
|
vbroadcasti32x2 291(%rax,%r14,8), %zmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1016(%rdx), %zmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x59,0x72,0x7f]
|
||||||
|
vbroadcasti32x2 1016(%rdx), %zmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1024(%rdx), %zmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x59,0xb2,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcasti32x2 1024(%rdx), %zmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1024(%rdx), %zmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x59,0x72,0x80]
|
||||||
|
vbroadcasti32x2 -1024(%rdx), %zmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1032(%rdx), %zmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x59,0xb2,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcasti32x2 -1032(%rdx), %zmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm17, %zmm20
|
||||||
|
// CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x59,0xe1]
|
||||||
|
vbroadcasti32x2 %xmm17, %zmm20
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm17, %zmm20 {%k1}
|
||||||
|
// CHECK: encoding: [0x62,0xa2,0x7d,0x49,0x59,0xe1]
|
||||||
|
vbroadcasti32x2 %xmm17, %zmm20 {%k1}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm17, %zmm20 {%k1} {z}
|
||||||
|
// CHECK: encoding: [0x62,0xa2,0x7d,0xc9,0x59,0xe1]
|
||||||
|
vbroadcasti32x2 %xmm17, %zmm20 {%k1} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 (%rcx), %zmm20
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x59,0x21]
|
||||||
|
vbroadcasti32x2 (%rcx), %zmm20
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 4660(%rax,%r14,8), %zmm20
|
||||||
|
// CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x59,0xa4,0xf0,0x34,0x12,0x00,0x00]
|
||||||
|
vbroadcasti32x2 4660(%rax,%r14,8), %zmm20
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1016(%rdx), %zmm20
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x59,0x62,0x7f]
|
||||||
|
vbroadcasti32x2 1016(%rdx), %zmm20
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1024(%rdx), %zmm20
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x59,0xa2,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcasti32x2 1024(%rdx), %zmm20
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1024(%rdx), %zmm20
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x59,0x62,0x80]
|
||||||
|
vbroadcasti32x2 -1024(%rdx), %zmm20
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1032(%rdx), %zmm20
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x59,0xa2,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcasti32x2 -1032(%rdx), %zmm20
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm23, %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x48,0x19,0xdf]
|
||||||
|
vbroadcastf32x2 %xmm23, %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm23, %zmm27 {%k6}
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x4e,0x19,0xdf]
|
||||||
|
vbroadcastf32x2 %xmm23, %zmm27 {%k6}
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm23, %zmm27 {%k6} {z}
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0xce,0x19,0xdf]
|
||||||
|
vbroadcastf32x2 %xmm23, %zmm27 {%k6} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 (%rcx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x19]
|
||||||
|
vbroadcastf32x2 (%rcx), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 291(%rax,%r14,8), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x48,0x19,0x9c,0xf0,0x23,0x01,0x00,0x00]
|
||||||
|
vbroadcastf32x2 291(%rax,%r14,8), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 1016(%rdx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x5a,0x7f]
|
||||||
|
vbroadcastf32x2 1016(%rdx), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 1024(%rdx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x9a,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcastf32x2 1024(%rdx), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 -1024(%rdx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x5a,0x80]
|
||||||
|
vbroadcastf32x2 -1024(%rdx), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 -1032(%rdx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x9a,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcastf32x2 -1032(%rdx), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm21, %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x48,0x19,0xdd]
|
||||||
|
vbroadcastf32x2 %xmm21, %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm21, %zmm27 {%k5}
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x4d,0x19,0xdd]
|
||||||
|
vbroadcastf32x2 %xmm21, %zmm27 {%k5}
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm21, %zmm27 {%k5} {z}
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0xcd,0x19,0xdd]
|
||||||
|
vbroadcastf32x2 %xmm21, %zmm27 {%k5} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 (%rcx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x19]
|
||||||
|
vbroadcastf32x2 (%rcx), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 4660(%rax,%r14,8), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x48,0x19,0x9c,0xf0,0x34,0x12,0x00,0x00]
|
||||||
|
vbroadcastf32x2 4660(%rax,%r14,8), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 1016(%rdx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x5a,0x7f]
|
||||||
|
vbroadcastf32x2 1016(%rdx), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 1024(%rdx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x9a,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcastf32x2 1024(%rdx), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 -1024(%rdx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x5a,0x80]
|
||||||
|
vbroadcastf32x2 -1024(%rdx), %zmm27
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 -1032(%rdx), %zmm27
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x19,0x9a,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcastf32x2 -1032(%rdx), %zmm27
|
||||||
|
|
||||||
|
|||||||
@ -4607,3 +4607,220 @@
|
|||||||
// CHECK: vfpclasspsl $123, -516(%rdx){1to8}, %k3
|
// CHECK: vfpclasspsl $123, -516(%rdx){1to8}, %k3
|
||||||
// CHECK: encoding: [0x62,0xf3,0x7d,0x38,0x66,0x9a,0xfc,0xfd,0xff,0xff,0x7b]
|
// CHECK: encoding: [0x62,0xf3,0x7d,0x38,0x66,0x9a,0xfc,0xfd,0xff,0xff,0x7b]
|
||||||
vfpclasspsl $0x7b,-516(%rdx){1to8}, %k3
|
vfpclasspsl $0x7b,-516(%rdx){1to8}, %k3
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm30, %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x08,0x59,0xf6]
|
||||||
|
vbroadcasti32x2 %xmm30, %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm30, %xmm30 {%k2}
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x0a,0x59,0xf6]
|
||||||
|
vbroadcasti32x2 %xmm30, %xmm30 {%k2}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm30, %xmm30 {%k2} {z}
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x8a,0x59,0xf6]
|
||||||
|
vbroadcasti32x2 %xmm30, %xmm30 {%k2} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 (%rcx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0x31]
|
||||||
|
vbroadcasti32x2 (%rcx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 291(%rax,%r14,8), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x08,0x59,0xb4,0xf0,0x23,0x01,0x00,0x00]
|
||||||
|
vbroadcasti32x2 291(%rax,%r14,8), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1016(%rdx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0x72,0x7f]
|
||||||
|
vbroadcasti32x2 1016(%rdx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1024(%rdx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0xb2,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcasti32x2 1024(%rdx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1024(%rdx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0x72,0x80]
|
||||||
|
vbroadcasti32x2 -1024(%rdx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1032(%rdx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0xb2,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcasti32x2 -1032(%rdx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm28, %ymm26
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x28,0x59,0xd4]
|
||||||
|
vbroadcasti32x2 %xmm28, %ymm26
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm28, %ymm26 {%k7}
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x2f,0x59,0xd4]
|
||||||
|
vbroadcasti32x2 %xmm28, %ymm26 {%k7}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm28, %ymm26 {%k7} {z}
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0xaf,0x59,0xd4]
|
||||||
|
vbroadcasti32x2 %xmm28, %ymm26 {%k7} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 (%rcx), %ymm26
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x59,0x11]
|
||||||
|
vbroadcasti32x2 (%rcx), %ymm26
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 291(%rax,%r14,8), %ymm26
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x28,0x59,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||||
|
vbroadcasti32x2 291(%rax,%r14,8), %ymm26
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1016(%rdx), %ymm26
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x59,0x52,0x7f]
|
||||||
|
vbroadcasti32x2 1016(%rdx), %ymm26
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1024(%rdx), %ymm26
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x59,0x92,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcasti32x2 1024(%rdx), %ymm26
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1024(%rdx), %ymm26
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x59,0x52,0x80]
|
||||||
|
vbroadcasti32x2 -1024(%rdx), %ymm26
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1032(%rdx), %ymm26
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x59,0x92,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcasti32x2 -1032(%rdx), %ymm26
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm28, %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x08,0x59,0xf4]
|
||||||
|
vbroadcasti32x2 %xmm28, %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm28, %xmm30 {%k6}
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x0e,0x59,0xf4]
|
||||||
|
vbroadcasti32x2 %xmm28, %xmm30 {%k6}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm28, %xmm30 {%k6} {z}
|
||||||
|
// CHECK: encoding: [0x62,0x02,0x7d,0x8e,0x59,0xf4]
|
||||||
|
vbroadcasti32x2 %xmm28, %xmm30 {%k6} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 (%rcx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0x31]
|
||||||
|
vbroadcasti32x2 (%rcx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 4660(%rax,%r14,8), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x08,0x59,0xb4,0xf0,0x34,0x12,0x00,0x00]
|
||||||
|
vbroadcasti32x2 4660(%rax,%r14,8), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1016(%rdx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0x72,0x7f]
|
||||||
|
vbroadcasti32x2 1016(%rdx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1024(%rdx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0xb2,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcasti32x2 1024(%rdx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1024(%rdx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0x72,0x80]
|
||||||
|
vbroadcasti32x2 -1024(%rdx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1032(%rdx), %xmm30
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x08,0x59,0xb2,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcasti32x2 -1032(%rdx), %xmm30
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm28, %ymm23
|
||||||
|
// CHECK: encoding: [0x62,0x82,0x7d,0x28,0x59,0xfc]
|
||||||
|
vbroadcasti32x2 %xmm28, %ymm23
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm28, %ymm23 {%k1}
|
||||||
|
// CHECK: encoding: [0x62,0x82,0x7d,0x29,0x59,0xfc]
|
||||||
|
vbroadcasti32x2 %xmm28, %ymm23 {%k1}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 %xmm28, %ymm23 {%k1} {z}
|
||||||
|
// CHECK: encoding: [0x62,0x82,0x7d,0xa9,0x59,0xfc]
|
||||||
|
vbroadcasti32x2 %xmm28, %ymm23 {%k1} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 (%rcx), %ymm23
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x59,0x39]
|
||||||
|
vbroadcasti32x2 (%rcx), %ymm23
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 4660(%rax,%r14,8), %ymm23
|
||||||
|
// CHECK: encoding: [0x62,0xa2,0x7d,0x28,0x59,0xbc,0xf0,0x34,0x12,0x00,0x00]
|
||||||
|
vbroadcasti32x2 4660(%rax,%r14,8), %ymm23
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1016(%rdx), %ymm23
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x59,0x7a,0x7f]
|
||||||
|
vbroadcasti32x2 1016(%rdx), %ymm23
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 1024(%rdx), %ymm23
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x59,0xba,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcasti32x2 1024(%rdx), %ymm23
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1024(%rdx), %ymm23
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x59,0x7a,0x80]
|
||||||
|
vbroadcasti32x2 -1024(%rdx), %ymm23
|
||||||
|
|
||||||
|
// CHECK: vbroadcasti32x2 -1032(%rdx), %ymm23
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x59,0xba,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcasti32x2 -1032(%rdx), %ymm23
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm18, %ymm28
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x28,0x19,0xe2]
|
||||||
|
vbroadcastf32x2 %xmm18, %ymm28
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm18, %ymm28 {%k7}
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x2f,0x19,0xe2]
|
||||||
|
vbroadcastf32x2 %xmm18, %ymm28 {%k7}
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm18, %ymm28 {%k7} {z}
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0xaf,0x19,0xe2]
|
||||||
|
vbroadcastf32x2 %xmm18, %ymm28 {%k7} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 (%rcx), %ymm28
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x19,0x21]
|
||||||
|
vbroadcastf32x2 (%rcx), %ymm28
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 291(%rax,%r14,8), %ymm28
|
||||||
|
// CHECK: encoding: [0x62,0x22,0x7d,0x28,0x19,0xa4,0xf0,0x23,0x01,0x00,0x00]
|
||||||
|
vbroadcastf32x2 291(%rax,%r14,8), %ymm28
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 1016(%rdx), %ymm28
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x19,0x62,0x7f]
|
||||||
|
vbroadcastf32x2 1016(%rdx), %ymm28
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 1024(%rdx), %ymm28
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x19,0xa2,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcastf32x2 1024(%rdx), %ymm28
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 -1024(%rdx), %ymm28
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x19,0x62,0x80]
|
||||||
|
vbroadcastf32x2 -1024(%rdx), %ymm28
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 -1032(%rdx), %ymm28
|
||||||
|
// CHECK: encoding: [0x62,0x62,0x7d,0x28,0x19,0xa2,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcastf32x2 -1032(%rdx), %ymm28
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm26, %ymm19
|
||||||
|
// CHECK: encoding: [0x62,0x82,0x7d,0x28,0x19,0xda]
|
||||||
|
vbroadcastf32x2 %xmm26, %ymm19
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm26, %ymm19 {%k7}
|
||||||
|
// CHECK: encoding: [0x62,0x82,0x7d,0x2f,0x19,0xda]
|
||||||
|
vbroadcastf32x2 %xmm26, %ymm19 {%k7}
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 %xmm26, %ymm19 {%k7} {z}
|
||||||
|
// CHECK: encoding: [0x62,0x82,0x7d,0xaf,0x19,0xda]
|
||||||
|
vbroadcastf32x2 %xmm26, %ymm19 {%k7} {z}
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 (%rcx), %ymm19
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x19,0x19]
|
||||||
|
vbroadcastf32x2 (%rcx), %ymm19
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 4660(%rax,%r14,8), %ymm19
|
||||||
|
// CHECK: encoding: [0x62,0xa2,0x7d,0x28,0x19,0x9c,0xf0,0x34,0x12,0x00,0x00]
|
||||||
|
vbroadcastf32x2 4660(%rax,%r14,8), %ymm19
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 1016(%rdx), %ymm19
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x19,0x5a,0x7f]
|
||||||
|
vbroadcastf32x2 1016(%rdx), %ymm19
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 1024(%rdx), %ymm19
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x19,0x9a,0x00,0x04,0x00,0x00]
|
||||||
|
vbroadcastf32x2 1024(%rdx), %ymm19
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 -1024(%rdx), %ymm19
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x19,0x5a,0x80]
|
||||||
|
vbroadcastf32x2 -1024(%rdx), %ymm19
|
||||||
|
|
||||||
|
// CHECK: vbroadcastf32x2 -1032(%rdx), %ymm19
|
||||||
|
// CHECK: encoding: [0x62,0xe2,0x7d,0x28,0x19,0x9a,0xf8,0xfb,0xff,0xff]
|
||||||
|
vbroadcastf32x2 -1032(%rdx), %ymm19
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user