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[AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics
Summary: Add buffer store/load 8/16 overloaded intrinsics for buffer, raw_buffer and struct_buffer Change-Id: I166a29f071b2ff4e4683fb0392564b1f223ac61d Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59265 llvm-svn: 356465
This commit is contained in:
Ryan Taylor
parent
52358ec746
commit
dd846d3872
@ -840,7 +840,7 @@ let TargetPrefix = "amdgcn" in {
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defset list<AMDGPURsrcIntrinsic> AMDGPUBufferIntrinsics = {
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class AMDGPUBufferLoad : Intrinsic <
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[llvm_anyfloat_ty],
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[llvm_any_ty],
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[llvm_v4i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // vindex(VGPR)
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llvm_i32_ty, // offset(SGPR/VGPR/imm)
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@ -861,7 +861,7 @@ def int_amdgcn_s_buffer_load : Intrinsic <
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class AMDGPUBufferStore : Intrinsic <
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[],
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[llvm_anyfloat_ty, // vdata(VGPR) -- can currently only select f32, v2f32, v4f32
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[llvm_any_ty, // vdata(VGPR)
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llvm_v4i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // vindex(VGPR)
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llvm_i32_ty, // offset(SGPR/VGPR/imm)
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@ -4208,10 +4208,16 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(ATOMIC_LOAD_FMIN)
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NODE_NAME_CASE(ATOMIC_LOAD_FMAX)
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NODE_NAME_CASE(BUFFER_LOAD)
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NODE_NAME_CASE(BUFFER_LOAD_UBYTE)
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NODE_NAME_CASE(BUFFER_LOAD_USHORT)
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NODE_NAME_CASE(BUFFER_LOAD_BYTE)
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NODE_NAME_CASE(BUFFER_LOAD_SHORT)
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NODE_NAME_CASE(BUFFER_LOAD_FORMAT)
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NODE_NAME_CASE(BUFFER_LOAD_FORMAT_D16)
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NODE_NAME_CASE(SBUFFER_LOAD)
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NODE_NAME_CASE(BUFFER_STORE)
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NODE_NAME_CASE(BUFFER_STORE_BYTE)
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NODE_NAME_CASE(BUFFER_STORE_SHORT)
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NODE_NAME_CASE(BUFFER_STORE_FORMAT)
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NODE_NAME_CASE(BUFFER_STORE_FORMAT_D16)
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NODE_NAME_CASE(BUFFER_ATOMIC_SWAP)
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@ -4376,6 +4382,14 @@ void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
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}
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break;
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}
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case AMDGPUISD::BUFFER_LOAD_UBYTE: {
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Known.Zero.setHighBits(24);
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break;
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}
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case AMDGPUISD::BUFFER_LOAD_USHORT: {
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Known.Zero.setHighBits(16);
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break;
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}
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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switch (IID) {
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@ -4421,6 +4435,14 @@ unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
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case AMDGPUISD::CARRY:
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case AMDGPUISD::BORROW:
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return 31;
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case AMDGPUISD::BUFFER_LOAD_BYTE:
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return 25;
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case AMDGPUISD::BUFFER_LOAD_SHORT:
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return 17;
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case AMDGPUISD::BUFFER_LOAD_UBYTE:
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return 24;
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case AMDGPUISD::BUFFER_LOAD_USHORT:
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return 16;
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case AMDGPUISD::FP_TO_FP16:
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case AMDGPUISD::FP16_ZEXT:
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return 16;
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@ -491,10 +491,16 @@ enum NodeType : unsigned {
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ATOMIC_LOAD_FMIN,
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ATOMIC_LOAD_FMAX,
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BUFFER_LOAD,
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BUFFER_LOAD_UBYTE,
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BUFFER_LOAD_USHORT,
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BUFFER_LOAD_BYTE,
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BUFFER_LOAD_SHORT,
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BUFFER_LOAD_FORMAT,
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BUFFER_LOAD_FORMAT_D16,
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SBUFFER_LOAD,
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BUFFER_STORE,
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BUFFER_STORE_BYTE,
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BUFFER_STORE_SHORT,
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BUFFER_STORE_FORMAT,
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BUFFER_STORE_FORMAT_D16,
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BUFFER_ATOMIC_SWAP,
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@ -1132,6 +1132,10 @@ defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2i32, "BUFFER_LOAD_DWORDX2">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v4f32, "BUFFER_LOAD_DWORDX4">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v4i32, "BUFFER_LOAD_DWORDX4">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_byte, i32, "BUFFER_LOAD_SBYTE">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_short, i32, "BUFFER_LOAD_SSHORT">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_ubyte, i32, "BUFFER_LOAD_UBYTE">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_ushort, i32, "BUFFER_LOAD_USHORT">;
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multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
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string opcode> {
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@ -1196,6 +1200,8 @@ defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v2i32, "BUFFER_STORE_DWORDX2">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v4f32, "BUFFER_STORE_DWORDX4">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v4i32, "BUFFER_STORE_DWORDX4">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_byte, i32, "BUFFER_STORE_BYTE">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_short, i32, "BUFFER_STORE_SHORT">;
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//===----------------------------------------------------------------------===//
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// buffer_atomic patterns
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@ -216,11 +216,15 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v8f16, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::BR_CC, MVT::i1, Expand);
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@ -677,6 +681,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::FCANONICALIZE);
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setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
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setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
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setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
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@ -5581,6 +5586,12 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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if (LoadVT.getScalarType() == MVT::f16)
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return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
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M, DAG, Ops);
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// Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
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if (LoadVT.getScalarType() == MVT::i8 ||
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LoadVT.getScalarType() == MVT::i16)
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return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
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return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
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M->getMemOperand());
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}
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@ -5609,6 +5620,12 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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if (LoadVT.getScalarType() == MVT::f16)
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return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
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M, DAG, Ops);
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// Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
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if (LoadVT.getScalarType() == MVT::i8 ||
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LoadVT.getScalarType() == MVT::i16)
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return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
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return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
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M->getMemOperand());
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}
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@ -5637,6 +5654,12 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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if (LoadVT.getScalarType() == MVT::f16)
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return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
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M, DAG, Ops);
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// Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
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if (LoadVT.getScalarType() == MVT::i8 ||
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LoadVT.getScalarType() == MVT::i16)
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return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
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return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
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M->getMemOperand());
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}
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@ -6207,6 +6230,12 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
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AMDGPUISD::BUFFER_STORE : AMDGPUISD::BUFFER_STORE_FORMAT;
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Opc = IsD16 ? AMDGPUISD::BUFFER_STORE_FORMAT_D16 : Opc;
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MemSDNode *M = cast<MemSDNode>(Op);
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// Handle BUFFER_STORE_BYTE/SHORT overloaded intrinsics
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EVT VDataType = VData.getValueType().getScalarType();
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if (VDataType == MVT::i8 || VDataType == MVT::i16)
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return handleByteShortBufferStores(DAG, VDataType, DL, Ops, M);
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return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
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M->getMemoryVT(), M->getMemOperand());
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}
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@ -6233,6 +6262,12 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
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AMDGPUISD::BUFFER_STORE : AMDGPUISD::BUFFER_STORE_FORMAT;
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Opc = IsD16 ? AMDGPUISD::BUFFER_STORE_FORMAT_D16 : Opc;
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MemSDNode *M = cast<MemSDNode>(Op);
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// Handle BUFFER_STORE_BYTE/SHORT overloaded intrinsics
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EVT VDataType = VData.getValueType().getScalarType();
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if (VDataType == MVT::i8 || VDataType == MVT::i16)
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return handleByteShortBufferStores(DAG, VDataType, DL, Ops, M);
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return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
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M->getMemoryVT(), M->getMemOperand());
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}
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@ -6259,6 +6294,12 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
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AMDGPUISD::BUFFER_STORE : AMDGPUISD::BUFFER_STORE_FORMAT;
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Opc = IsD16 ? AMDGPUISD::BUFFER_STORE_FORMAT_D16 : Opc;
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MemSDNode *M = cast<MemSDNode>(Op);
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// Handle BUFFER_STORE_BYTE/SHORT overloaded intrinsics
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EVT VDataType = VData.getValueType().getScalarType();
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if (VDataType == MVT::i8 || VDataType == MVT::i16)
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return handleByteShortBufferStores(DAG, VDataType, DL, Ops, M);
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return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
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M->getMemoryVT(), M->getMemOperand());
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}
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@ -6361,6 +6402,38 @@ void SITargetLowering::setBufferOffsets(SDValue CombinedOffset,
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Offsets[2] = DAG.getConstant(0, DL, MVT::i32);
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}
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// Handle 8 bit and 16 bit buffer loads
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SDValue SITargetLowering::handleByteShortBufferLoads(SelectionDAG &DAG,
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EVT LoadVT, SDLoc DL,
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ArrayRef<SDValue> Ops,
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MemSDNode *M) const {
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EVT IntVT = LoadVT.changeTypeToInteger();
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unsigned Opc = (LoadVT.getScalarType() == MVT::i8) ?
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AMDGPUISD::BUFFER_LOAD_UBYTE : AMDGPUISD::BUFFER_LOAD_USHORT;
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SDVTList ResList = DAG.getVTList(MVT::i32, MVT::Other);
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SDValue BufferLoad = DAG.getMemIntrinsicNode(Opc, DL, ResList,
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Ops, IntVT,
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M->getMemOperand());
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SDValue BufferLoadTrunc = DAG.getNode(ISD::TRUNCATE, DL,
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LoadVT.getScalarType(), BufferLoad);
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return DAG.getMergeValues({BufferLoadTrunc, BufferLoad.getValue(1)}, DL);
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}
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// Handle 8 bit and 16 bit buffer stores
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SDValue SITargetLowering::handleByteShortBufferStores(SelectionDAG &DAG,
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EVT VDataType, SDLoc DL,
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SDValue Ops[],
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MemSDNode *M) const {
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SDValue BufferStoreExt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Ops[1]);
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Ops[1] = BufferStoreExt;
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unsigned Opc = (VDataType == MVT::i8) ? AMDGPUISD::BUFFER_STORE_BYTE :
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AMDGPUISD::BUFFER_STORE_SHORT;
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ArrayRef<SDValue> OpsRef = makeArrayRef(&Ops[0], 9);
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return DAG.getMemIntrinsicNode(Opc, DL, M->getVTList(), OpsRef, VDataType,
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M->getMemOperand());
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}
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static SDValue getLoadExtOrTrunc(SelectionDAG &DAG,
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ISD::LoadExtType ExtType, SDValue Op,
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const SDLoc &SL, EVT VT) {
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@ -7692,6 +7765,43 @@ SDValue SITargetLowering::performZeroExtendCombine(SDNode *N,
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return SDValue();
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}
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SDValue SITargetLowering::performSignExtendInRegCombine(SDNode *N,
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DAGCombinerInfo &DCI)
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const {
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SDValue Src = N->getOperand(0);
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auto *VTSign = cast<VTSDNode>(N->getOperand(1));
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if (((Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_UBYTE &&
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VTSign->getVT() == MVT::i8) ||
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(Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_USHORT &&
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VTSign->getVT() == MVT::i16)) &&
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Src.hasOneUse()) {
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auto *M = cast<MemSDNode>(Src);
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SDValue Ops[] = {
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Src.getOperand(0), // Chain
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Src.getOperand(1), // rsrc
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Src.getOperand(2), // vindex
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Src.getOperand(3), // voffset
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Src.getOperand(4), // soffset
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Src.getOperand(5), // offset
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Src.getOperand(6),
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Src.getOperand(7)
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};
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// replace with BUFFER_LOAD_BYTE/SHORT
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SDVTList ResList = DCI.DAG.getVTList(MVT::i32,
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Src.getOperand(0).getValueType());
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unsigned Opc = (Src.getOpcode() == AMDGPUISD::BUFFER_LOAD_UBYTE) ?
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AMDGPUISD::BUFFER_LOAD_BYTE : AMDGPUISD::BUFFER_LOAD_SHORT;
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SDValue BufferLoadSignExt = DCI.DAG.getMemIntrinsicNode(Opc, SDLoc(N),
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ResList,
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Ops, M->getMemoryVT(),
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M->getMemOperand());
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return DCI.DAG.getMergeValues({BufferLoadSignExt,
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BufferLoadSignExt.getValue(1)}, SDLoc(N));
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}
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return SDValue();
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}
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SDValue SITargetLowering::performClassCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -8940,7 +9050,6 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
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return SDValue();
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switch (N->getOpcode()) {
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default:
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return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
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@ -9007,6 +9116,8 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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return performXorCombine(N, DCI);
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case ISD::ZERO_EXTEND:
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return performZeroExtendCombine(N, DCI);
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case ISD::SIGN_EXTEND_INREG:
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return performSignExtendInRegCombine(N , DCI);
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case AMDGPUISD::FP_CLASS:
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return performClassCombine(N, DCI);
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case ISD::FCANONICALIZE:
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@ -140,6 +140,7 @@ private:
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SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
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const APFloat &C) const;
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@ -192,6 +193,15 @@ private:
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void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
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SDValue *Offsets, unsigned Align = 4) const;
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// Handle 8 bit and 16 bit buffer loads
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SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
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ArrayRef<SDValue> Ops, MemSDNode *M) const;
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// Handle 8 bit and 16 bit buffer stores
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SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
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SDLoc DL, SDValue Ops[],
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MemSDNode *M) const;
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public:
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SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
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@ -127,6 +127,14 @@ def SDTBufferLoad : SDTypeProfile<1, 7,
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def SIbuffer_load : SDNode <"AMDGPUISD::BUFFER_LOAD", SDTBufferLoad,
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[SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
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def SIbuffer_load_ubyte : SDNode <"AMDGPUISD::BUFFER_LOAD_UBYTE", SDTBufferLoad,
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[SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
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def SIbuffer_load_ushort : SDNode <"AMDGPUISD::BUFFER_LOAD_USHORT", SDTBufferLoad,
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[SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
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def SIbuffer_load_byte : SDNode <"AMDGPUISD::BUFFER_LOAD_BYTE", SDTBufferLoad,
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[SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
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def SIbuffer_load_short: SDNode <"AMDGPUISD::BUFFER_LOAD_SHORT", SDTBufferLoad,
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[SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
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def SIbuffer_load_format : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT", SDTBufferLoad,
|
||||
[SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
|
||||
def SIbuffer_load_format_d16 : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT_D16",
|
||||
@ -145,6 +153,12 @@ def SDTBufferStore : SDTypeProfile<0, 8,
|
||||
|
||||
def SIbuffer_store : SDNode <"AMDGPUISD::BUFFER_STORE", SDTBufferStore,
|
||||
[SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
|
||||
def SIbuffer_store_byte: SDNode <"AMDGPUISD::BUFFER_STORE_BYTE",
|
||||
SDTBufferStore,
|
||||
[SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
|
||||
def SIbuffer_store_short : SDNode <"AMDGPUISD::BUFFER_STORE_SHORT",
|
||||
SDTBufferStore,
|
||||
[SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
|
||||
def SIbuffer_store_format : SDNode <"AMDGPUISD::BUFFER_STORE_FORMAT",
|
||||
SDTBufferStore,
|
||||
[SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
|
||||
|
||||
@ -257,9 +257,194 @@ main_body:
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_ubyte:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_ubyte(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%val = uitofp i8 %tmp to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_ushort:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0 offset:16
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_ushort(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 16, i1 0, i1 0)
|
||||
%tmp2 = zext i16 %tmp to i32
|
||||
%val = uitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_sbyte:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_sbyte(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = sext i8 %tmp to i32
|
||||
%val = sitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_sshort:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0 offset:16
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_sshort(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 16, i1 0, i1 0)
|
||||
%tmp2 = sext i16 %tmp to i32
|
||||
%val = sitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_ubyte_bitcast:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_ubyte_bitcast(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = zext i8 %tmp to i32
|
||||
%val = bitcast i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_ushort_bitcast:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_ushort_bitcast(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = zext i16 %tmp to i32
|
||||
%val = bitcast i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_sbyte_bitcast:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_sbyte_bitcast(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = sext i8 %tmp to i32
|
||||
%val = bitcast i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_sshort_bitcast:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_sshort_bitcast(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = sext i16 %tmp to i32
|
||||
%val = bitcast i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_ubyte_mul_bitcast:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_mul_u32_u24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}}
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_ubyte_mul_bitcast(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = zext i8 %tmp to i32
|
||||
%tmp3 = mul i32 %tmp2, 255
|
||||
%val = bitcast i32 %tmp3 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_ushort_mul_bitcast:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_mul_u32_u24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}}
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_ushort_mul_bitcast(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = zext i16 %tmp to i32
|
||||
%tmp3 = mul i32 %tmp2, 255
|
||||
%val = bitcast i32 %tmp3 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_sbyte_mul_bitcast:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_mul_i32_i24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}}
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_sbyte_mul_bitcast(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = sext i8 %tmp to i32
|
||||
%tmp3 = mul i32 %tmp2, 255
|
||||
%val = bitcast i32 %tmp3 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_sshort_mul_bitcast:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_mul_i32_i24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}}
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_sshort_mul_bitcast(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = sext i16 %tmp to i32
|
||||
%tmp3 = mul i32 %tmp2, 255
|
||||
%val = bitcast i32 %tmp3 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_load_sbyte_type_check:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_bfe_i32 v{{[0-9]}}, v{{[0-9]}}, 0, 5
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @buffer_load_sbyte_type_check(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
%tmp2 = zext i8 %tmp to i32
|
||||
%tmp3 = shl i32 %tmp2, 27
|
||||
%tmp4 = ashr i32 %tmp3, 27
|
||||
%val = bitcast i32 %tmp4 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
|
||||
declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #0
|
||||
declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #0
|
||||
declare i8 @llvm.amdgcn.buffer.load.i8(<4 x i32>, i32, i32, i1, i1) #0
|
||||
declare i16 @llvm.amdgcn.buffer.load.i16(<4 x i32>, i32, i32, i1, i1) #0
|
||||
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
||||
|
||||
attributes #0 = { nounwind readonly }
|
||||
|
||||
@ -233,9 +233,35 @@ define amdgpu_ps void @buffer_store_x3_offset_merged3(<4 x i32> inreg %rsrc, <2
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_store_byte:
|
||||
;CHECK-NOT: s_waitcnt
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK: buffer_store_byte v{{[0-9]}}, off, s[0:3], 0 offset:8
|
||||
define amdgpu_ps void @buffer_store_byte(<4 x i32> inreg %rsrc, float %v1) {
|
||||
main_body:
|
||||
%v2 = fptoui float %v1 to i32
|
||||
%v3 = trunc i32 %v2 to i8
|
||||
call void @llvm.amdgcn.buffer.store.i8(i8 %v3, <4 x i32> %rsrc, i32 0, i32 8, i1 0, i1 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_store_short:
|
||||
;CHECK-NOT: s_waitcnt
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK: buffer_store_short v{{[0-9]}}, off, s[0:3], 0 offset:16
|
||||
define amdgpu_ps void @buffer_store_short(<4 x i32> inreg %rsrc, float %v1) {
|
||||
main_body:
|
||||
%v2 = fptoui float %v1 to i32
|
||||
%v3 = trunc i32 %v2 to i16
|
||||
call void @llvm.amdgcn.buffer.store.i16(i16 %v3, <4 x i32> %rsrc, i32 0, i32 16, i1 0, i1 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #0
|
||||
declare void @llvm.amdgcn.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #0
|
||||
declare void @llvm.amdgcn.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #0
|
||||
declare void @llvm.amdgcn.buffer.store.i8(i8, <4 x i32>, i32, i32, i1, i1) #0
|
||||
declare void @llvm.amdgcn.buffer.store.i16(i16, <4 x i32>, i32, i32, i1, i1) #0
|
||||
declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
|
||||
@ -263,6 +263,62 @@ main_body:
|
||||
ret {<4 x float>, <2 x float>, float} %r2
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}raw_buffer_load_ubyte:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0
|
||||
;CHECK: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @raw_buffer_load_ubyte(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
||||
%tmp2 = zext i8 %tmp to i32
|
||||
%val = uitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}raw_buffer_load_ushort:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @raw_buffer_load_ushort(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
||||
%tmp2 = zext i16 %tmp to i32
|
||||
%val = uitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}raw_buffer_load_sbyte:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @raw_buffer_load_sbyte(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
||||
%tmp2 = sext i8 %tmp to i32
|
||||
%val = sitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}raw_buffer_load_sshort:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @raw_buffer_load_sshort(<4 x i32> inreg %rsrc) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
||||
%tmp2 = sext i16 %tmp to i32
|
||||
%val = sitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32) #0
|
||||
declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32) #0
|
||||
declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32) #0
|
||||
@ -270,5 +326,7 @@ declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #0
|
||||
declare <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32>, i32, i32, i32) #0
|
||||
declare <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32>, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
||||
declare i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32>, i32, i32, i32) #0
|
||||
declare i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32>, i32, i32, i32) #0
|
||||
|
||||
attributes #0 = { nounwind readonly }
|
||||
|
||||
@ -189,6 +189,32 @@ main_body:
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}raw_buffer_store_byte:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: v_cvt_u32_f32_e32 v{{[0-9]}}, v{{[0-9]}}
|
||||
;CHECK-NEXT: buffer_store_byte v{{[0-9]}}, off, s[0:3], 0
|
||||
;CHECK-NEXT: s_endpgm
|
||||
define amdgpu_ps void @raw_buffer_store_byte(<4 x i32> inreg %rsrc, float %v1) {
|
||||
main_body:
|
||||
%v2 = fptoui float %v1 to i32
|
||||
%v3 = trunc i32 %v2 to i8
|
||||
call void @llvm.amdgcn.raw.buffer.store.i8(i8 %v3, <4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}raw_buffer_store_short:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: v_cvt_u32_f32_e32 v{{[0-9]}}, v{{[0-9]}}
|
||||
;CHECK-NEXT: buffer_store_short v{{[0-9]}}, off, s[0:3], 0
|
||||
;CHECK-NEXT: s_endpgm
|
||||
define amdgpu_ps void @raw_buffer_store_short(<4 x i32> inreg %rsrc, float %v1) {
|
||||
main_body:
|
||||
%v2 = fptoui float %v1 to i32
|
||||
%v3 = trunc i32 %v2 to i16
|
||||
call void @llvm.amdgcn.raw.buffer.store.i16(i16 %v3, <4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32) #0
|
||||
@ -196,6 +222,8 @@ declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) #0
|
||||
declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32) #1
|
||||
declare void @llvm.amdgcn.raw.buffer.store.i8(i8, <4 x i32>, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.raw.buffer.store.i16(i16, <4 x i32>, i32, i32, i32) #0
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readonly }
|
||||
|
||||
@ -144,6 +144,62 @@ main_body:
|
||||
ret {<4 x float>, <2 x float>, float} %r2
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}struct_buffer_load_ubyte:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
|
||||
;CHECK: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @struct_buffer_load_ubyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
|
||||
%tmp2 = zext i8 %tmp to i32
|
||||
%val = uitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}struct_buffer_load_ushort:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @struct_buffer_load_ushort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
|
||||
%tmp2 = zext i16 %tmp to i32
|
||||
%val = uitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}struct_buffer_load_sbyte:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @struct_buffer_load_sbyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
|
||||
main_body:
|
||||
%tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
|
||||
%tmp2 = sext i8 %tmp to i32
|
||||
%val = sitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}struct_buffer_load_sshort:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
|
||||
;CHECK-NEXT: s_waitcnt vmcnt(0)
|
||||
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
|
||||
;CHECK-NEXT: ; return to shader part epilog
|
||||
define amdgpu_ps float @struct_buffer_load_sshort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
|
||||
main_body:
|
||||
%tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
|
||||
%tmp2 = sext i16 %tmp to i32
|
||||
%val = sitofp i32 %tmp2 to float
|
||||
ret float %val
|
||||
}
|
||||
|
||||
declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32) #0
|
||||
declare <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32>, i32, i32, i32, i32) #0
|
||||
declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #0
|
||||
@ -151,5 +207,7 @@ declare i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32>, i32, i32, i32, i32) #
|
||||
declare <2 x i32> @llvm.amdgcn.struct.buffer.load.v2i32(<4 x i32>, i32, i32, i32, i32) #0
|
||||
declare <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32>, i32, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
||||
declare i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32>, i32, i32, i32, i32) #0
|
||||
declare i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32>, i32, i32, i32, i32) #0
|
||||
|
||||
attributes #0 = { nounwind readonly }
|
||||
|
||||
@ -108,6 +108,32 @@ main_body:
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}struct_buffer_store_byte:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: v_cvt_u32_f32_e32 v{{[0-9]}}, v{{[0-9]}}
|
||||
;CHECK-NEXT: buffer_store_byte v{{[0-9]}}, v{{[0-9]}}, s[0:3], 0 idxen
|
||||
;CHECK-NEXT: s_endpgm
|
||||
define amdgpu_ps void @struct_buffer_store_byte(<4 x i32> inreg %rsrc, float %v1, i32 %index) {
|
||||
main_body:
|
||||
%v2 = fptoui float %v1 to i32
|
||||
%v3 = trunc i32 %v2 to i8
|
||||
call void @llvm.amdgcn.struct.buffer.store.i8(i8 %v3, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}struct_buffer_store_short:
|
||||
;CHECK-NEXT: %bb.
|
||||
;CHECK-NEXT: v_cvt_u32_f32_e32 v{{[0-9]}}, v{{[0-9]}}
|
||||
;CHECK-NEXT: buffer_store_short v{{[0-9]}}, v{{[0-9]}}, s[0:3], 0 idxen
|
||||
;CHECK-NEXT: s_endpgm
|
||||
define amdgpu_ps void @struct_buffer_store_short(<4 x i32> inreg %rsrc, float %v1, i32 %index) {
|
||||
main_body:
|
||||
%v2 = fptoui float %v1 to i32
|
||||
%v3 = trunc i32 %v2 to i16
|
||||
call void @llvm.amdgcn.struct.buffer.store.i16(i16 %v3, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.struct.buffer.store.f32(float, <4 x i32>, i32, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.struct.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32) #0
|
||||
@ -115,6 +141,8 @@ declare void @llvm.amdgcn.struct.buffer.store.i32(i32, <4 x i32>, i32, i32, i32,
|
||||
declare void @llvm.amdgcn.struct.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.struct.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32) #0
|
||||
declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #1
|
||||
declare void @llvm.amdgcn.struct.buffer.store.i8(i8, <4 x i32>, i32, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.struct.buffer.store.i16(i16, <4 x i32>, i32, i32, i32, i32) #0
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readonly }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user