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https://github.com/RPCS3/llvm-mirror.git
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[MIPS GlobalISel] Lower G_UADDE and narrowScalar G_ADD
Lower G_UADDE and legalize G_ADD using narrowScalar on MIPS32. Differential Revision: https://reviews.llvm.org/D54580 llvm-svn: 349346
This commit is contained in:
Petar Avramovic
parent
ff2cabbc44
commit
df2c4df13c
@ -1119,6 +1119,24 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
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case TargetOpcode::G_CTTZ:
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case TargetOpcode::G_CTPOP:
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return lowerBitCount(MI, TypeIdx, Ty);
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case G_UADDE: {
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unsigned Res = MI.getOperand(0).getReg();
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unsigned CarryOut = MI.getOperand(1).getReg();
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unsigned LHS = MI.getOperand(2).getReg();
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unsigned RHS = MI.getOperand(3).getReg();
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unsigned CarryIn = MI.getOperand(4).getReg();
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unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
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unsigned ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildAdd(TmpRes, LHS, RHS);
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MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
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MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
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MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
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MI.eraseFromParent();
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return Legalized;
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}
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}
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}
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@ -20,14 +20,16 @@ using namespace llvm;
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MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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using namespace TargetOpcode;
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const LLT s1 = LLT::scalar(1);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT p0 = LLT::pointer(0, 32);
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getActionDefinitionsBuilder(G_ADD)
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.legalFor({s32})
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.minScalar(0, s32)
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.customFor({s64});
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_UADDE)
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.lowerFor({{s32, s1}});
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getActionDefinitionsBuilder({G_LOAD, G_STORE})
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.legalForCartesianProduct({p0, s32}, {p0});
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@ -66,33 +68,6 @@ bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
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MIRBuilder.setInstr(MI);
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switch (MI.getOpcode()) {
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case G_ADD: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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const LLT sHalf = LLT::scalar(Size / 2);
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unsigned RHSLow = MRI.createGenericVirtualRegister(sHalf);
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unsigned RHSHigh = MRI.createGenericVirtualRegister(sHalf);
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unsigned LHSLow = MRI.createGenericVirtualRegister(sHalf);
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unsigned LHSHigh = MRI.createGenericVirtualRegister(sHalf);
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unsigned ResLow = MRI.createGenericVirtualRegister(sHalf);
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unsigned ResHigh = MRI.createGenericVirtualRegister(sHalf);
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unsigned Carry = MRI.createGenericVirtualRegister(sHalf);
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unsigned TmpResHigh = MRI.createGenericVirtualRegister(sHalf);
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MIRBuilder.buildUnmerge({RHSLow, RHSHigh}, MI.getOperand(2).getReg());
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MIRBuilder.buildUnmerge({LHSLow, LHSHigh}, MI.getOperand(1).getReg());
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MIRBuilder.buildAdd(TmpResHigh, LHSHigh, RHSHigh);
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MIRBuilder.buildAdd(ResLow, LHSLow, RHSLow);
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MIRBuilder.buildICmp(CmpInst::ICMP_ULT, Carry, ResLow, LHSLow);
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MIRBuilder.buildAdd(ResHigh, TmpResHigh, Carry);
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {ResLow, ResHigh});
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MI.eraseFromParent();
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break;
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}
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default:
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return false;
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}
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@ -10,6 +10,7 @@
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define void @add_i16_zext() {entry: ret void}
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define void @add_i16_aext() {entry: ret void}
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define void @add_i64() {entry: ret void}
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define void @add_i128() {entry: ret void}
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...
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---
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@ -226,11 +227,19 @@ body: |
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
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; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]]
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY1]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
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; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]]
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; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[COPY3]]
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; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[ICMP]]
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; MIPS32: $v0 = COPY [[ADD2]](s32)
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; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
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; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]]
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; MIPS32: $v0 = COPY [[ADD3]](s32)
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; MIPS32: $v1 = COPY [[ADD1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%2:_(s32) = COPY $a0
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@ -246,3 +255,82 @@ body: |
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RetRA implicit $v0, implicit $v1
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...
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---
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name: add_i128
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alignment: 2
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, offset: 28, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
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- { id: 1, offset: 24, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
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- { id: 2, offset: 20, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
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- { id: 3, offset: 16, size: 4, alignment: 8, stack-id: 0, isImmutable: true }
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: add_i128
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 0)
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; MIPS32: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
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; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1, align 0)
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; MIPS32: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2
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; MIPS32: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p0) :: (load 4 from %fixed-stack.2, align 0)
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; MIPS32: [[FRAME_INDEX3:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.3
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; MIPS32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p0) :: (load 4 from %fixed-stack.3, align 0)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[COPY]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
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; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[AND]]
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; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[LOAD]]
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; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
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; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ADD2]], [[AND1]]
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; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[LOAD1]]
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; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
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; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
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; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND2]]
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; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD5]](s32), [[LOAD2]]
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; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
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; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
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; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
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; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[AND3]]
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; MIPS32: $v0 = COPY [[ADD1]](s32)
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; MIPS32: $v1 = COPY [[ADD3]](s32)
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; MIPS32: $a0 = COPY [[ADD5]](s32)
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; MIPS32: $a1 = COPY [[ADD7]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
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%2:_(s32) = COPY $a0
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%3:_(s32) = COPY $a1
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%4:_(s32) = COPY $a2
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%5:_(s32) = COPY $a3
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%0:_(s128) = G_MERGE_VALUES %2(s32), %3(s32), %4(s32), %5(s32)
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%10:_(p0) = G_FRAME_INDEX %fixed-stack.3
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%6:_(s32) = G_LOAD %10(p0) :: (load 4 from %fixed-stack.3, align 0)
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%11:_(p0) = G_FRAME_INDEX %fixed-stack.2
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%7:_(s32) = G_LOAD %11(p0) :: (load 4 from %fixed-stack.2, align 0)
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%12:_(p0) = G_FRAME_INDEX %fixed-stack.1
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%8:_(s32) = G_LOAD %12(p0) :: (load 4 from %fixed-stack.1, align 0)
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%13:_(p0) = G_FRAME_INDEX %fixed-stack.0
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%9:_(s32) = G_LOAD %13(p0) :: (load 4 from %fixed-stack.0, align 0)
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%1:_(s128) = G_MERGE_VALUES %6(s32), %7(s32), %8(s32), %9(s32)
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%14:_(s128) = G_ADD %1, %0
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%15:_(s32), %16:_(s32), %17:_(s32), %18:_(s32) = G_UNMERGE_VALUES %14(s128)
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$v0 = COPY %15(s32)
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$v1 = COPY %16(s32)
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$a0 = COPY %17(s32)
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$a1 = COPY %18(s32)
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RetRA implicit $v0, implicit $v1, implicit $a0, implicit $a1
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...
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@ -90,14 +90,73 @@ entry:
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define i64 @add_i64(i64 %a, i64 %b) {
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; MIPS32-LABEL: add_i64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: addu $5, $7, $5
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; MIPS32-NEXT: lui $1, 0
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; MIPS32-NEXT: ori $1, $1, 0
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; MIPS32-NEXT: addu $4, $6, $4
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; MIPS32-NEXT: sltu $6, $4, $6
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; MIPS32-NEXT: addu $3, $5, $6
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; MIPS32-NEXT: move $2, $4
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; MIPS32-NEXT: lui $2, 0
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; MIPS32-NEXT: ori $2, $2, 1
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; MIPS32-NEXT: and $1, $1, $2
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; MIPS32-NEXT: addu $1, $4, $1
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; MIPS32-NEXT: sltu $2, $1, $6
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; MIPS32-NEXT: addu $4, $7, $5
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; MIPS32-NEXT: lui $5, 0
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; MIPS32-NEXT: ori $5, $5, 1
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; MIPS32-NEXT: and $2, $2, $5
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; MIPS32-NEXT: addu $3, $4, $2
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; MIPS32-NEXT: move $2, $1
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%add = add i64 %b, %a
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ret i64 %add
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}
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}
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define i128 @add_i128(i128 %a, i128 %b) {
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; MIPS32-LABEL: add_i128:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: addiu $sp, $sp, -8
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; MIPS32-NEXT: .cfi_def_cfa_offset 8
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; MIPS32-NEXT: addiu $1, $sp, 24
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; MIPS32-NEXT: lw $1, 0($1)
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; MIPS32-NEXT: addiu $2, $sp, 28
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; MIPS32-NEXT: lw $2, 0($2)
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; MIPS32-NEXT: addiu $3, $sp, 32
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; MIPS32-NEXT: lw $3, 0($3)
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; MIPS32-NEXT: addiu $8, $sp, 36
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; MIPS32-NEXT: lw $8, 0($8)
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; MIPS32-NEXT: lui $9, 0
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; MIPS32-NEXT: ori $9, $9, 0
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; MIPS32-NEXT: addu $4, $1, $4
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; MIPS32-NEXT: lui $10, 0
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; MIPS32-NEXT: ori $10, $10, 1
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; MIPS32-NEXT: and $9, $9, $10
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; MIPS32-NEXT: addu $4, $4, $9
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; MIPS32-NEXT: sltu $1, $4, $1
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; MIPS32-NEXT: addu $5, $2, $5
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; MIPS32-NEXT: lui $9, 0
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; MIPS32-NEXT: ori $9, $9, 1
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; MIPS32-NEXT: and $1, $1, $9
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; MIPS32-NEXT: addu $1, $5, $1
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; MIPS32-NEXT: sltu $2, $1, $2
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; MIPS32-NEXT: addu $5, $3, $6
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; MIPS32-NEXT: lui $6, 0
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; MIPS32-NEXT: ori $6, $6, 1
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; MIPS32-NEXT: and $2, $2, $6
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; MIPS32-NEXT: addu $2, $5, $2
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; MIPS32-NEXT: sltu $3, $2, $3
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; MIPS32-NEXT: addu $5, $8, $7
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; MIPS32-NEXT: lui $6, 0
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; MIPS32-NEXT: ori $6, $6, 1
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; MIPS32-NEXT: and $3, $3, $6
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; MIPS32-NEXT: addu $5, $5, $3
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; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
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; MIPS32-NEXT: move $2, $4
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; MIPS32-NEXT: move $3, $1
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; MIPS32-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
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; MIPS32-NEXT: addiu $sp, $sp, 8
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%add = add i128 %b, %a
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ret i128 %add
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}
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