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Minor cleanup related to my latest scheduler changes.
llvm-svn: 122545
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c926e98fc7
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@ -328,7 +328,7 @@ namespace llvm {
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/// isInstr - Return true if this SUnit refers to a machine instruction as
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/// opposed to an SDNode.
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bool isInstr() const { return !Node; }
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bool isInstr() const { return Instr; }
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/// setInstr - Assign the instruction for the SUnit.
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/// This may be used during post-regalloc scheduling.
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@ -348,7 +348,10 @@ void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) {
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/// Check to see if any of the pending instructions are ready to issue. If
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/// so, add them to the available queue.
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void ScheduleDAGRRList::ReleasePending() {
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assert(!EnableSchedCycles && "requires --enable-sched-cycles" );
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if (!EnableSchedCycles) {
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assert(PendingQueue.empty() && "pending instrs not allowed in this mode");
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return;
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}
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// If the available queue is empty, it is safe to reset MinAvailableCycle.
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if (AvailableQueue->empty())
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@ -634,8 +637,7 @@ void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) {
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RestoreHazardCheckerBottomUp();
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if (EnableSchedCycles)
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ReleasePending();
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ReleasePending();
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++NumBacktracks;
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}
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