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[TargetLowering] SimplifyDemandedVectorElts - support MUL and ANY_EXTEND_VECTOR_INREG
Also fold ANY_EXTEND_VECTOR_INREG -> BITCAST if we only need the bottom element. Fixes temporary regression introduced in rL363693. llvm-svn: 363694
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@ -2156,6 +2156,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
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}
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break;
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}
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case ISD::ANY_EXTEND_VECTOR_INREG:
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case ISD::SIGN_EXTEND_VECTOR_INREG:
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case ISD::ZERO_EXTEND_VECTOR_INREG: {
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APInt SrcUndef, SrcZero;
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@ -2168,6 +2169,13 @@ bool TargetLowering::SimplifyDemandedVectorElts(
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KnownZero = SrcZero.zextOrTrunc(NumElts);
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KnownUndef = SrcUndef.zextOrTrunc(NumElts);
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if (Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&
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Op.getValueSizeInBits() == Src.getValueSizeInBits() &&
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DemandedSrcElts == 1 && TLO.DAG.getDataLayout().isLittleEndian()) {
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// aext - if we just need the bottom element then we can bitcast.
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return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
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}
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if (Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
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// zext(undef) upper bits are guaranteed to be zero.
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if (DemandedElts.isSubsetOf(KnownUndef))
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@ -2201,6 +2209,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
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KnownUndef = getKnownUndefForVectorBinop(Op, TLO.DAG, UndefLHS, UndefRHS);
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break;
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}
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case ISD::MUL:
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case ISD::AND: {
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APInt SrcUndef, SrcZero;
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if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, SrcUndef,
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@ -1837,7 +1837,6 @@ define i8 @test_v16i8(<16 x i8> %a0) {
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; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpackuswb %xmm0, %xmm0, %xmm1
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; AVX2-NEXT: vpsrlw $8, %xmm1, %xmm1
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; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
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; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpextrb $0, %xmm0, %eax
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; AVX2-NEXT: # kill: def $al killed $al killed $eax
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