RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-18 11:20:03 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[mips][microMIPS] Revert commit r267137

Browse Source 
Commit r267137 was the reason for failing tests in LLVM test suite.

llvm-svn: 267419
This commit is contained in:
Hrvoje Varga 2016-04-25 15:40:08 +00:00
parent eabfffce01
commit e25aaa57ef
10 changed files with 5 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -969,9 +969,7 @@ class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
MMR6Arch<"addu16"> {
int AddedComplexity = 1;
}
MMR6Arch<"addu16">;
class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
MMR6Arch<"and16">;
class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,

1
lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -278,6 +278,7 @@ class MOVEP_FM_MM16 {
class MMArch {
string Arch = "micromips";
list<dag> Pattern = [];
}
class ADD_FM_MM<bits<6> op, bits<10> funct> : MMArch {

4
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -988,8 +988,6 @@ def : MipsPat<(load addrimm4lsl2:$addr),
def : MipsPat<(load addr:$addr),
(LW_MM addr:$addr)>;
defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
//===----------------------------------------------------------------------===//
// MicroMips instruction aliases
//===----------------------------------------------------------------------===//
@ -1025,6 +1023,4 @@ def : MipsInstAlias<"tltu $rs, $rt",
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tne $rs, $rt",
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"slt $rs, $rt, $imm",
(SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
}

8
lib/Target/Mips/MipsInstrInfo.td
View File

@ -1648,11 +1648,11 @@ def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
}
def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd>, ADDI_FM<0x8>,
ISA_MIPS1_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
SLTI_FM<0xa>;
def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
SLTI_FM<0xb>;
let AdditionalPredicates = [NotInMicroMips] in {
def ANDi : MMRel, StdMMR6Rel,
ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
ADDI_FM<0xc>;
@ -1676,10 +1676,8 @@ def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
let AdditionalPredicates = [NotInMicroMips] in {
def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
}
let AdditionalPredicates = [NotInMicroMips] in {
def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
ADD_FM<0, 0x24>;
@ -2190,11 +2188,9 @@ def : MipsInstAlias<"negu $rt",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
def : MipsInstAlias<"negu $rt, $rs",
(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
let Predicates = [NotInMicroMips] in {
def : MipsInstAlias<
"slt $rs, $rt, $imm",
(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
}
def : MipsInstAlias<
"sltu $rt, $rs, $imm",
(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
@ -2572,12 +2568,10 @@ multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
(XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
}
let AdditionalPredicates = [NotInMicroMips] in {
defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
defm : SetlePats<GPR32, SLT, SLTu>;
defm : SetgtPats<GPR32, SLT, SLTu>;
defm : SetgePats<GPR32, SLT, SLTu>;
}
defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
// bswap pattern

2
test/CodeGen/Mips/brconlt.ll
View File

@ -1,5 +1,4 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
@i = global i32 5, align 4
@j = global i32 10, align 4
@ -14,7 +13,6 @@ entry:
br i1 %cmp, label %if.end, label %if.then
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
; MM32R6: slt ${{[0-9]+}}, ${{[0-9]+}}
; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
; 16: $[[LABEL]]:

2
test/CodeGen/Mips/seteq.ll
View File

@ -1,5 +1,4 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
@ -16,7 +15,6 @@ entry:
store i32 %conv, i32* @r1, align 4
; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
; 16: move ${{[0-9]+}}, $24
ret void
}

6
test/CodeGen/Mips/setltk.ll
View File

@ -1,5 +1,4 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
@j = global i32 -5, align 4
@k = global i32 10, align 4
@ -15,8 +14,7 @@ entry:
%cmp = icmp slt i32 %0, 10
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @r1, align 4
; 16: slti $[[REGISTER:[0-9]+]], 10
; MM32R6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
; 16: move $[[REGISTER]], $24
; 16: slti $[[REGISTER:[0-9]+]], 10
; 16: move $[[REGISTER]], $24
ret void
}

2
test/CodeGen/Mips/setne.ll
View File

@ -1,5 +1,4 @@
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
@ -16,7 +15,6 @@ entry:
store i32 %conv, i32* @r1, align 4
; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
; MMR6: sltu ${{[0-9]+}}, $zero, ${{[0-9]+}}
; 16: move ${{[0-9]+}}, $24
ret void
}

4
test/MC/Disassembler/Mips/micromips32r6/valid.txt
View File

@ -258,10 +258,6 @@
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x00 0xa4 0x1b 0x50 # CHECK: slt $3, $4, $5
0x90 0x64 0x01 0x00 # CHECK: slti $3, $4, 256
0xb0 0x64 0x01 0x00 # CHECK: sltiu $3, $4, 256
0x00 0xa4 0x1b 0x90 # CHECK: sltu $3, $4, $5
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
0x00 0x00 0x47 0x7c # CHECK: di

4
test/MC/Mips/micromips32r6/valid.s
View File

@ -260,10 +260,6 @@
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
slt $3, $4, $5 # CHECK: slt $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x50]
slti $3, $4, 256 # CHECK: slti $3, $4, 256 # encoding: [0x90,0x64,0x01,0x00]
sltiu $3, $4, 256 # CHECK: sltiu $3, $4, 256 # encoding: [0xb0,0x64,0x01,0x00]
sltu $3, $4, $5 # CHECK: sltu $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x90]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]