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Described the missing AVX forms of SSE2 convert instructions
llvm-svn: 107108
This commit is contained in:
Bruno Cardoso Lopes
parent
2a4e6d0e34
commit
e4809f15bf
@ -944,6 +944,17 @@ defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
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/// SSE 2 Only
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// Convert scalar double to scalar single
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let isAsmParserOnly = 1 in {
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def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
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(ins FR64:$src1, FR64:$src2),
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"cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
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VEX_4V;
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def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
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(ins FR64:$src1, f64mem:$src2),
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"vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, XD, Requires<[HasAVX, HasSSE2, OptForSize]>, VEX_4V;
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}
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def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
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"cvtsd2ss\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround FR64:$src))]>;
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@ -952,12 +963,27 @@ def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
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[(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
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Requires<[HasSSE2, OptForSize]>;
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def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
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def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
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let isAsmParserOnly = 1 in
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defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
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int_x86_sse2_cvtsd2ss, f64mem, load,
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"cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
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XS, VEX_4V;
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let Constraints = "$src1 = $dst" in
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defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
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int_x86_sse2_cvtsd2ss, f64mem, load,
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"cvtsd2ss\t{$src2, $dst|$dst, $src2}">, XS;
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// SSE2 instructions with XS prefix
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// Convert scalar single to scalar double
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let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
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def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
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(ins FR32:$src1, FR32:$src2),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, XS, Requires<[HasAVX, HasSSE2]>, VEX_4V;
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def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
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(ins FR32:$src1, f32mem:$src2),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, XS, VEX_4V, Requires<[HasAVX, HasSSE2, OptForSize]>;
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}
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def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
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"cvtss2sd\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fextend FR32:$src))]>, XS,
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@ -967,118 +993,21 @@ def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
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[(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
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Requires<[HasSSE2, OptForSize]>;
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def : Pat<(extloadf32 addr:$src),
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(CVTSS2SDrr (MOVSSrm addr:$src))>,
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Requires<[HasSSE2, OptForSpeed]>;
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// SSE2 instructions without OpSize prefix
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def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
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TB, Requires<[HasSSE2]>;
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def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps
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(bitconvert (memopv2i64 addr:$src))))]>,
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TB, Requires<[HasSSE2]>;
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// SSE2 instructions with XS prefix
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def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd
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(bitconvert (memopv2i64 addr:$src))))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
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def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq
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(memop addr:$src)))]>;
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// SSE2 packed instructions with XS prefix
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def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
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def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
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def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(int_x86_sse2_cvttps2dq VR128:$src))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvttps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttps2dq
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(memop addr:$src)))]>,
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XS, Requires<[HasSSE2]>;
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// SSE2 packed instructions with XD prefix
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def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
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XD, Requires<[HasSSE2]>;
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def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
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(memop addr:$src)))]>,
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XD, Requires<[HasSSE2]>;
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def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvttpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
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def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
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"cvttpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
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(memop addr:$src)))]>;
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// SSE2 instructions without OpSize prefix
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def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
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def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
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def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
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TB, Requires<[HasSSE2]>;
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def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
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"cvtps2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd
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(load addr:$src)))]>,
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TB, Requires<[HasSSE2]>;
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def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
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def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
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def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
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def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
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(memop addr:$src)))]>;
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// Match intrinsics which expect XMM operand(s).
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// Aliases for intrinsics
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let Constraints = "$src1 = $dst" in {
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def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
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VR128:$src2))]>;
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def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
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"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
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(load addr:$src2)))]>;
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let isAsmParserOnly = 1 in {
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def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
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VR128:$src2))]>, XS, VEX_4V,
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Requires<[HasAVX, HasSSE2]>;
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def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
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"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
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(load addr:$src2)))]>, XS, VEX_4V,
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Requires<[HasAVX, HasSSE2]>;
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}
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let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
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def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
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"cvtss2sd\t{$src2, $dst|$dst, $src2}",
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@ -1093,6 +1022,229 @@ def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
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Requires<[HasSSE2]>;
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}
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def : Pat<(extloadf32 addr:$src),
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(CVTSS2SDrr (MOVSSrm addr:$src))>,
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Requires<[HasSSE2, OptForSpeed]>;
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// Convert doubleword to packed single/double fp
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let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
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def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
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TB, VEX, Requires<[HasAVX, HasSSE2]>;
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def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"vcvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps
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(bitconvert (memopv2i64 addr:$src))))]>,
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TB, VEX, Requires<[HasAVX, HasSSE2]>;
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}
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def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
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TB, Requires<[HasSSE2]>;
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def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps
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(bitconvert (memopv2i64 addr:$src))))]>,
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TB, Requires<[HasSSE2]>;
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// FIXME: why the non-intrinsic version is described as SSE3?
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let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
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def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
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XS, VEX, Requires<[HasAVX, HasSSE2]>;
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def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"vcvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd
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(bitconvert (memopv2i64 addr:$src))))]>,
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XS, VEX, Requires<[HasAVX, HasSSE2]>;
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}
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def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
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XS, Requires<[HasSSE2]>;
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def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"cvtdq2pd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd
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(bitconvert (memopv2i64 addr:$src))))]>,
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XS, Requires<[HasSSE2]>;
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// Convert packed single/double fp to doubleword
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let isAsmParserOnly = 1 in {
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def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
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def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
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}
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def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
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def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
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let isAsmParserOnly = 1 in {
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def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
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VEX;
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def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
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(ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq
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(memop addr:$src)))]>, VEX;
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}
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def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
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def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtps2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq
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(memop addr:$src)))]>;
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let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
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def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"vcvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
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XD, VEX, Requires<[HasAVX, HasSSE2]>;
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def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"vcvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
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(memop addr:$src)))]>,
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XD, VEX, Requires<[HasAVX, HasSSE2]>;
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}
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def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtpd2dq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
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XD, Requires<[HasSSE2]>;
|
||||
def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvtpd2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
|
||||
(memop addr:$src)))]>,
|
||||
XD, Requires<[HasSSE2]>;
|
||||
|
||||
|
||||
// Convert with truncation packed single/double fp to doubleword
|
||||
let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
|
||||
def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
|
||||
def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
|
||||
}
|
||||
def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
|
||||
def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
|
||||
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"vcvttps2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_sse2_cvttps2dq VR128:$src))]>,
|
||||
XS, VEX, Requires<[HasAVX, HasSSE2]>;
|
||||
def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"vcvttps2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvttps2dq
|
||||
(memop addr:$src)))]>,
|
||||
XS, VEX, Requires<[HasAVX, HasSSE2]>;
|
||||
}
|
||||
def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvttps2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_sse2_cvttps2dq VR128:$src))]>,
|
||||
XS, Requires<[HasSSE2]>;
|
||||
def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvttps2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvttps2dq
|
||||
(memop addr:$src)))]>,
|
||||
XS, Requires<[HasSSE2]>;
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src),
|
||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
|
||||
VEX;
|
||||
def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins f128mem:$src),
|
||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
|
||||
(memop addr:$src)))]>, VEX;
|
||||
}
|
||||
def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
|
||||
def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
|
||||
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
|
||||
(memop addr:$src)))]>;
|
||||
|
||||
// Convert packed single to packed double
|
||||
let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
|
||||
def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
|
||||
Requires<[HasAVX]>;
|
||||
def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
||||
"vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
|
||||
Requires<[HasAVX]>;
|
||||
}
|
||||
def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
|
||||
def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
||||
"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
|
||||
VEX, Requires<[HasAVX, HasSSE2]>;
|
||||
def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
||||
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtps2pd
|
||||
(load addr:$src)))]>,
|
||||
VEX, Requires<[HasAVX, HasSSE2]>;
|
||||
}
|
||||
def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
|
||||
TB, Requires<[HasSSE2]>;
|
||||
def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
||||
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtps2pd
|
||||
(load addr:$src)))]>,
|
||||
TB, Requires<[HasSSE2]>;
|
||||
|
||||
// Convert packed double to packed single
|
||||
let isAsmParserOnly = 1 in {
|
||||
def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
|
||||
// FIXME: the memory form of this instruction should described using
|
||||
// use extra asm syntax
|
||||
}
|
||||
def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
|
||||
def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
|
||||
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
|
||||
def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins f128mem:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
|
||||
(memop addr:$src)))]>;
|
||||
}
|
||||
def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
|
||||
def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
|
||||
(memop addr:$src)))]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SSE 1 & 2 - Compare Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -1722,9 +1874,6 @@ let isCommutable = 0 in {
|
||||
///
|
||||
/// And, we have a special variant form for a full-vector intrinsic form.
|
||||
///
|
||||
/// These four forms can each have a reg or a mem operand, so there are a
|
||||
/// total of eight "instructions".
|
||||
///
|
||||
multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode,
|
||||
Intrinsic F32Int,
|
||||
|
||||
@ -10822,3 +10822,54 @@
|
||||
// CHECK: encoding: [0xc5,0xf8,0x5b,0x30]
|
||||
vcvtdq2ps (%eax), %xmm6
|
||||
|
||||
// CHECK: vcvtsd2ss %xmm2, %xmm4, %xmm6
|
||||
// CHECK: encoding: [0xc5,0xdb,0x5a,0xf2]
|
||||
vcvtsd2ss %xmm2, %xmm4, %xmm6
|
||||
|
||||
// CHECK: vcvtsd2ss (%eax), %xmm4, %xmm6
|
||||
// CHECK: encoding: [0xc5,0xdb,0x5a,0x30]
|
||||
vcvtsd2ss (%eax), %xmm4, %xmm6
|
||||
|
||||
// CHECK: vcvtps2dq %xmm2, %xmm3
|
||||
// CHECK: encoding: [0xc5,0xf9,0x5b,0xda]
|
||||
vcvtps2dq %xmm2, %xmm3
|
||||
|
||||
// CHECK: vcvtps2dq (%eax), %xmm3
|
||||
// CHECK: encoding: [0xc5,0xf9,0x5b,0x18]
|
||||
vcvtps2dq (%eax), %xmm3
|
||||
|
||||
// CHECK: vcvtss2sd %xmm2, %xmm4, %xmm6
|
||||
// CHECK: encoding: [0xc5,0xda,0x5a,0xf2]
|
||||
vcvtss2sd %xmm2, %xmm4, %xmm6
|
||||
|
||||
// CHECK: vcvtss2sd (%eax), %xmm4, %xmm6
|
||||
// CHECK: encoding: [0xc5,0xda,0x5a,0x30]
|
||||
vcvtss2sd (%eax), %xmm4, %xmm6
|
||||
|
||||
// CHECK: vcvtdq2ps %xmm4, %xmm6
|
||||
// CHECK: encoding: [0xc5,0xf8,0x5b,0xf4]
|
||||
vcvtdq2ps %xmm4, %xmm6
|
||||
|
||||
// CHECK: vcvtdq2ps (%ecx), %xmm4
|
||||
// CHECK: encoding: [0xc5,0xf8,0x5b,0x21]
|
||||
vcvtdq2ps (%ecx), %xmm4
|
||||
|
||||
// CHECK: vcvttps2dq %xmm2, %xmm3
|
||||
// CHECK: encoding: [0xc5,0xfa,0x5b,0xda]
|
||||
vcvttps2dq %xmm2, %xmm3
|
||||
|
||||
// CHECK: vcvttps2dq (%eax), %xmm3
|
||||
// CHECK: encoding: [0xc5,0xfa,0x5b,0x18]
|
||||
vcvttps2dq (%eax), %xmm3
|
||||
|
||||
// CHECK: vcvtps2pd %xmm2, %xmm3
|
||||
// CHECK: encoding: [0xc5,0xf8,0x5a,0xda]
|
||||
vcvtps2pd %xmm2, %xmm3
|
||||
|
||||
// CHECK: vcvtps2pd (%eax), %xmm3
|
||||
// CHECK: encoding: [0xc5,0xf8,0x5a,0x18]
|
||||
vcvtps2pd (%eax), %xmm3
|
||||
|
||||
// CHECK: vcvtpd2ps %xmm2, %xmm3
|
||||
// CHECK: encoding: [0xc5,0xf9,0x5a,0xda]
|
||||
vcvtpd2ps %xmm2, %xmm3
|
||||
|
||||
@ -870,3 +870,55 @@ pshufb CPI1_0(%rip), %xmm1
|
||||
// CHECK: encoding: [0xc5,0x78,0x5b,0x20]
|
||||
vcvtdq2ps (%rax), %xmm12
|
||||
|
||||
// CHECK: vcvtsd2ss %xmm12, %xmm13, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x13,0x5a,0xd4]
|
||||
vcvtsd2ss %xmm12, %xmm13, %xmm10
|
||||
|
||||
// CHECK: vcvtsd2ss (%rax), %xmm13, %xmm10
|
||||
// CHECK: encoding: [0xc5,0x13,0x5a,0x10]
|
||||
vcvtsd2ss (%rax), %xmm13, %xmm10
|
||||
|
||||
// CHECK: vcvtps2dq %xmm12, %xmm11
|
||||
// CHECK: encoding: [0xc4,0x41,0x79,0x5b,0xdc]
|
||||
vcvtps2dq %xmm12, %xmm11
|
||||
|
||||
// CHECK: vcvtps2dq (%rax), %xmm11
|
||||
// CHECK: encoding: [0xc5,0x79,0x5b,0x18]
|
||||
vcvtps2dq (%rax), %xmm11
|
||||
|
||||
// CHECK: vcvtss2sd %xmm12, %xmm13, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x12,0x5a,0xd4]
|
||||
vcvtss2sd %xmm12, %xmm13, %xmm10
|
||||
|
||||
// CHECK: vcvtss2sd (%rax), %xmm13, %xmm10
|
||||
// CHECK: encoding: [0xc5,0x12,0x5a,0x10]
|
||||
vcvtss2sd (%rax), %xmm13, %xmm10
|
||||
|
||||
// CHECK: vcvtdq2ps %xmm13, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x41,0x78,0x5b,0xd5]
|
||||
vcvtdq2ps %xmm13, %xmm10
|
||||
|
||||
// CHECK: vcvtdq2ps (%ecx), %xmm13
|
||||
// CHECK: encoding: [0xc5,0x78,0x5b,0x29]
|
||||
vcvtdq2ps (%ecx), %xmm13
|
||||
|
||||
// CHECK: vcvttps2dq %xmm12, %xmm11
|
||||
// CHECK: encoding: [0xc4,0x41,0x7a,0x5b,0xdc]
|
||||
vcvttps2dq %xmm12, %xmm11
|
||||
|
||||
// CHECK: vcvttps2dq (%rax), %xmm11
|
||||
// CHECK: encoding: [0xc5,0x7a,0x5b,0x18]
|
||||
vcvttps2dq (%rax), %xmm11
|
||||
|
||||
// CHECK: vcvtps2pd %xmm12, %xmm11
|
||||
// CHECK: encoding: [0xc4,0x41,0x78,0x5a,0xdc]
|
||||
vcvtps2pd %xmm12, %xmm11
|
||||
|
||||
// CHECK: vcvtps2pd (%rax), %xmm11
|
||||
// CHECK: encoding: [0xc5,0x78,0x5a,0x18]
|
||||
vcvtps2pd (%rax), %xmm11
|
||||
|
||||
// CHECK: vcvtpd2ps %xmm12, %xmm11
|
||||
// CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xdc]
|
||||
vcvtpd2ps %xmm12, %xmm11
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user