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Explicitly pass in debug location information to BuildMI.

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llvm-svn: 63599
This commit is contained in:
Bill Wendling 2009-02-03 02:29:34 +00:00
parent 14bc9010d5
commit e496361cf5
4 changed files with 6 additions and 4 deletions
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3
lib/CodeGen/GCStrategy.cpp
View File

@ -329,7 +329,8 @@ void MachineCodeAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
unsigned MachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
unsigned Label = MMI->NextLabelID();
BuildMI(MBB, MI, TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label);
BuildMI(MBB, MI, MI->getDebugLoc(),
TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label);
return Label;
}

2
lib/CodeGen/PHIElimination.cpp
View File

@ -166,7 +166,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
if (isSourceDefinedByImplicitDef(MPhi, MRI))
// If all sources of a PHI node are implicit_def, just emit an
// implicit_def instead of a copy.
BuildMI(MBB, AfterPHIsIt,
BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
else {
IncomingReg = MF.getRegInfo().createVirtualRegister(RC);

2
lib/CodeGen/TargetInstrInfoImpl.cpp
View File

@ -44,7 +44,7 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
bool Reg0IsDead = MI->getOperand(0).isDead();
MachineFunction &MF = *MI->getParent()->getParent();
return BuildMI(MF, MI->getDesc())
return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
.addReg(Reg0, true, false, false, Reg0IsDead)
.addReg(Reg2, false, false, Reg2IsKill)
.addReg(Reg1, false, false, Reg1IsKill);

3
lib/CodeGen/VirtRegMap.cpp
View File

@ -1360,7 +1360,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
MI.getOperand(i).setReg(RReg);
if (VRM.isImplicitlyDefined(VirtReg))
BuildMI(MBB, &MI, TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
BuildMI(MBB, &MI, MI.getDebugLoc(),
TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
continue;
}