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https://github.com/RPCS3/llvm-mirror.git
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[ARM] Fix for DLS/LE CodeGen
The expensive buildbots highlighted the mir tests were broken, which I've now updated and added --verify-machineinstrs to them. This also uncovered a couple of bugs in the backend pass, so these have also been fixed. llvm-svn: 364323
This commit is contained in:
Sam Parker
parent
bbd7a470db
commit
e6d16f9670
@ -74,8 +74,8 @@ INITIALIZE_PASS(ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME,
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false, false)
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bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &MF) {
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//if (!static_cast<const ARMSubtarget&>(MF.getSubtarget()).hasLOB())
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//return false;
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if (!static_cast<const ARMSubtarget&>(MF.getSubtarget()).hasLOB())
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return false;
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LLVM_DEBUG(dbgs() << "ARM Loops on " << MF.getName() << " ------------- \n");
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@ -133,16 +133,15 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
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Dec = &MI;
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else if (MI.getOpcode() == ARM::t2LoopEnd)
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End = &MI;
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else if (MI.getDesc().isCall())
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// TODO: Though the call will require LE to execute again, does this
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// mean we should revert? Always executing LE hopefully should be
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// faster than performing a sub,cmp,br or even subs,br.
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Revert = true;
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if (!Dec)
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continue;
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// TODO: Though the call will require LE to execute again, does this
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// mean we should revert? Always executing LE hopefully should be faster
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// than performing a sub,cmp,br or even subs,br.
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if (MI.getDesc().isCall())
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Revert = true;
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// If we find that we load/store LR between LoopDec and LoopEnd, expect
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// that the decremented value has been spilled to the stack. Because
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// this value isn't actually going to be produced until the latch, by LE,
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@ -272,11 +271,13 @@ void ARMLowOverheadLoops::Expand(MachineLoop *ML, MachineInstr *Start,
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MIB.addReg(ARM::LR);
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MIB.addImm(0);
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MIB.addImm(ARMCC::AL);
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MIB.addReg(ARM::CPSR);
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// Create bne
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MIB = BuildMI(*MBB, End, End->getDebugLoc(), TII->get(ARM::t2Bcc));
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MIB.add(End->getOperand(1)); // branch target
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MIB.addImm(ARMCC::NE); // condition code
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MIB.addReg(ARM::CPSR);
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End->eraseFromParent();
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Dec->eraseFromParent();
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};
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@ -1,18 +1,14 @@
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# RUN: llc -mtriple=thumbv8.1m.main %s -o - | FileCheck %s
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# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
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# CHECK: .LBB0_2:
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# CHECK: sub.w lr, lr, #1
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# CHECK: mov [[TMP:r[0-9]+]], lr
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# CHECK: bl bar
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# CHECK: mov lr, [[TMP]]
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# CHECK: cmp.w lr, #0
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# CHECK: bne{{.*}} .LBB0_2
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# CHECK: while.body:
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# CHECK-NOT: t2DLS
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# CHECK-NOT: t2LEUpdate
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-arm-none-eabi"
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define i32 @skip_call(i32 %n) #0 {
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define i32 @skip_spill(i32 %n) #0 {
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entry:
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%cmp6 = icmp eq i32 %n, 0
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br i1 %cmp6, label %while.end, label %while.body.preheader
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@ -38,7 +34,6 @@
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declare i32 @bar(...) local_unnamed_addr #0
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declare void @llvm.set.loop.iterations.i32(i32) #1
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
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declare void @llvm.stackprotector(i8*, i8**) #2
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attributes #0 = { "target-features"="+mve.fp" }
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attributes #1 = { noduplicate nounwind }
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@ -46,14 +41,14 @@
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...
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---
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name: skip_call
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name: skip_spill
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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tracksRegLiveness: false
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hasWinCFI: false
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registers: []
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liveins:
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@ -95,47 +90,41 @@ constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x30000000), %bb.3(0x50000000)
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liveins: $r0, $r4, $r5, $r7, $lr
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successors: %bb.4(0x30000000), %bb.1(0x50000000)
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$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr
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frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 16
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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frame-setup CFI_INSTRUCTION offset $r5, -12
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frame-setup CFI_INSTRUCTION offset $r4, -16
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t2CMPri $r0, 0, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.1, 0, killed $cpsr
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tCBZ $r0, %bb.4
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bb.3.while.body.preheader:
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successors: %bb.4(0x80000000)
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liveins: $r0
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bb.1.while.body.preheader:
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successors: %bb.2(0x80000000)
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$lr = tMOVr $r0, 14, $noreg
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renamable $r4 = t2MOVi 0, 14, $noreg, $noreg
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renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
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t2DoLoopStart killed $r0
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bb.4.while.body:
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successors: %bb.4(0x7c000000), %bb.2(0x04000000)
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liveins: $lr, $r4
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bb.2.while.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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renamable $lr = t2LoopDec killed renamable $lr, 1
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$r5 = tMOVr killed $lr, 14, $noreg
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tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0
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$lr = tMOVr killed $r5, 14, $noreg
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renamable $r4 = nsw t2ADDrr killed renamable $r0, killed renamable $r4, 14, $noreg, $noreg
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t2LoopEnd renamable $lr, %bb.4
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t2B %bb.2, 14, $noreg
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bb.2.while.end:
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liveins: $r4
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renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2LoopEnd renamable $lr, %bb.2
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tB %bb.3, 14, $noreg
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bb.3.while.end:
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$r0 = tMOVr killed $r4, 14, $noreg
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$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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bb.1:
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renamable $r4 = t2MOVi 0, 14, $noreg, $noreg
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bb.4:
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renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = tMOVr killed $r4, 14, $noreg
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$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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...
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@ -1,11 +1,8 @@
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# RUN: llc -mtriple=thumbv8.1m.main %s -o - | FileCheck %s
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# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
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# CHECK: .LBB0_2:
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# CHECK: sub.w lr, lr, #1
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# CHECK: str.w lr, [sp, #12]
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# CHECK: ldr.w lr, [sp, #12]
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# CHECK: cmp.w lr, #0
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# CHECK: bne{{.*}} .LBB0_2
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# CHECK: while.body:
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# CHECK-NOT: t2DLS
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# CHECK-NOT: t2LEUpdate
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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@ -37,7 +34,6 @@
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declare i32 @bar(...) local_unnamed_addr #0
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declare void @llvm.set.loop.iterations.i32(i32) #1
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
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declare void @llvm.stackprotector(i8*, i8**) #2
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attributes #0 = { "target-features"="+mve.fp" }
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attributes #1 = { noduplicate nounwind }
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@ -52,7 +48,7 @@ legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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tracksRegLiveness: false
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hasWinCFI: false
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registers: []
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liveins:
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@ -94,46 +90,41 @@ constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x30000000), %bb.3(0x50000000)
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liveins: $r0, $r4, $r5, $r7, $lr
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successors: %bb.4(0x30000000), %bb.1(0x50000000)
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$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr
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frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 16
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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frame-setup CFI_INSTRUCTION offset $r5, -12
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frame-setup CFI_INSTRUCTION offset $r4, -16
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t2CMPri $r0, 0, 14, $noreg, implicit-def $cpsr
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t2Bcc %bb.1, 0, killed $cpsr
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tCBZ $r0, %bb.4
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bb.3.while.body.preheader:
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successors: %bb.4(0x80000000)
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liveins: $r0
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bb.1.while.body.preheader:
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successors: %bb.2(0x80000000)
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$lr = tMOVr $r0, 14, $noreg
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renamable $r4 = t2MOVi 0, 14, $noreg, $noreg
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renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
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t2DoLoopStart killed $r0
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bb.4.while.body:
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successors: %bb.4(0x7c000000), %bb.2(0x04000000)
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liveins: $lr, $r4
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bb.2.while.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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$r5 = tMOVr killed $lr, 14, $noreg
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tBL 14, $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0
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$lr = tMOVr killed $r5, 14, $noreg
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renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r0, 14, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2STRi12 $lr, %stack.0, 0, 14, $noreg :: (store 4)
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$lr = t2LDRi12 %stack.0, 0, 14, $noreg :: (load 4)
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renamable $r4 = nsw t2ADDrr renamable $lr, killed renamable $r4, 14, $noreg, $noreg
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t2LoopEnd renamable $lr, %bb.4
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t2B %bb.2, 14, $noreg
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bb.2.while.end:
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liveins: $r4
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t2LoopEnd renamable $lr, %bb.2
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tB %bb.3, 14, $noreg
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bb.3.while.end:
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$r0 = tMOVr killed $r4, 14, $noreg
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$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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bb.1:
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renamable $r4 = t2MOVi 0, 14, $noreg, $noreg
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bb.4:
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renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = tMOVr killed $r4, 14, $noreg
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$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
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...
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