RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-04-04 00:31:54 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix LivePhysRegs::addLiveOuts

Browse Source 
Summary:
The testing for returnBB was flipped which may cause ARM ld/st opt pass uses callee saved regs in returnBB when shrink-wrap is used.


Reviewers: t.p.northover, apazos, MatzeB

Subscribers: mcrosier, zzheng, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D16434

llvm-svn: 258569
This commit is contained in:
Weiming Zhao 2016-01-22 22:21:34 +00:00
parent 40baae90ce
commit e73494fde9
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/LivePhysRegs.cpp
View File

@ -151,7 +151,7 @@ void LivePhysRegs::addLiveOuts(const MachineBasicBlock *MBB,
if (AddPristinesAndCSRs) { if (AddPristinesAndCSRs) {
const MachineFunction &MF = *MBB->getParent(); const MachineFunction &MF = *MBB->getParent();
addPristines(*this, MF, *TRI); addPristines(*this, MF, *TRI);
if (!MBB->isReturnBlock()) { if (MBB->isReturnBlock()) {
// The return block has no successors whose live-ins we could merge // The return block has no successors whose live-ins we could merge
// below. So instead we add the callee saved registers manually. // below. So instead we add the callee saved registers manually.
for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I)