RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-29 15:04:57 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Don't forego folding of loads into 64-bit adds when the other

Browse Source 
operand is a signed 32-bit immediate. Unlike with the 8-bit
signed immediate case, it isn't actually smaller to fold a
32-bit signed immediate instead of a load. In fact, it's
larger in the case of 32-bit unsigned immediates, because
they can be materialized with movl instead of movq.

llvm-svn: 67001
This commit is contained in:
Dan Gohman 2009-03-14 02:07:16 +00:00
parent 2cdac55ad0
commit e7495ef7aa
1 changed files with 3 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -319,16 +319,9 @@ bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
// addl 4(%esp), %eax
// The former is 2 bytes shorter. In case where the increment is 1, then
// the saving can be 4 bytes (by using incl %eax).
ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(U->getOperand(1));
if (Imm) {
if (U->getValueType(0) == MVT::i64) {
if ((int32_t)Imm->getZExtValue() == (int64_t)Imm->getZExtValue())
return false;
} else {
if ((int8_t)Imm->getZExtValue() == (int64_t)Imm->getZExtValue())
return false;
}
}
if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(U->getOperand(1)))
if (Imm->getAPIntValue().isSignedIntN(8))
return false;
}
}