mirror of
https://github.com/RPCS3/llvm-mirror.git
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PTX: Handle FrameIndex nodes
llvm-svn: 140532
This commit is contained in:
Justin Holewinski
parent
90ed5fdd4f
commit
e79db83e87
@ -295,9 +295,9 @@ void PTXAsmPrinter::EmitFunctionBodyStart() {
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for (unsigned i = 0, e = FrameInfo->getNumObjects(); i != e; ++i) {
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DEBUG(dbgs() << "Size of object: " << FrameInfo->getObjectSize(i) << "\n");
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if (FrameInfo->getObjectSize(i) > 0) {
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std::string def = "\t.reg .b";
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std::string def = "\t.local .b";
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def += utostr(FrameInfo->getObjectSize(i)*8); // Convert to bits
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def += " s";
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def += " __local_";
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def += utostr(i);
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def += ";";
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OutStreamer.EmitRawText(Twine(def));
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@ -37,6 +37,7 @@ class PTXDAGToDAGISel : public SelectionDAGISel {
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bool SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDValue &Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRii(SDValue &Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRlocal(SDValue &Addr, SDValue &Base, SDValue &Offset);
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// Include the pieces auto'gened from the target description
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#include "PTXGenDAGISel.inc"
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@ -48,6 +49,7 @@ class PTXDAGToDAGISel : public SelectionDAGISel {
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SDNode *SelectREADPARAM(SDNode *Node);
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SDNode *SelectWRITEPARAM(SDNode *Node);
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SDNode *SelectFrameIndex(SDNode *Node);
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bool isImm(const SDValue &operand);
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bool SelectImm(const SDValue &operand, SDValue &imm);
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@ -75,6 +77,8 @@ SDNode *PTXDAGToDAGISel::Select(SDNode *Node) {
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return SelectREADPARAM(Node);
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case PTXISD::WRITE_PARAM:
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return SelectWRITEPARAM(Node);
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case ISD::FrameIndex:
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return SelectFrameIndex(Node);
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default:
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return SelectCode(Node);
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}
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@ -173,6 +177,25 @@ SDNode *PTXDAGToDAGISel::SelectWRITEPARAM(SDNode *Node) {
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return Ret;
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}
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SDNode *PTXDAGToDAGISel::SelectFrameIndex(SDNode *Node) {
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int FI = cast<FrameIndexSDNode>(Node)->getIndex();
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//dbgs() << "Selecting FrameIndex at index " << FI << "\n";
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, Node->getValueType(0));
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//unsigned OpCode = PTX::LOAD_LOCAL_F32;
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//for (SDNode::use_iterator i = Node->use_begin(), e = Node->use_end();
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// i != e; ++i) {
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// SDNode *Use = *i;
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// dbgs() << "USE: ";
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// Use->dumpr(CurDAG);
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//}
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return Node;
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//return CurDAG->getMachineNode(OpCode, Node->getDebugLoc(),
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// Node->getValueType(0), TFI);
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}
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// Match memory operand of the form [reg+reg]
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bool PTXDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1, SDValue &R2) {
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if (Addr.getOpcode() != ISD::ADD || Addr.getNumOperands() < 2 ||
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@ -243,6 +266,41 @@ bool PTXDAGToDAGISel::SelectADDRii(SDValue &Addr, SDValue &Base,
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return false;
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}
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// Match memory operand of the form [reg], [imm+reg], and [reg+imm]
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bool PTXDAGToDAGISel::SelectADDRlocal(SDValue &Addr, SDValue &Base,
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SDValue &Offset) {
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if (Addr.getOpcode() != ISD::ADD) {
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// let SelectADDRii handle the [imm] case
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if (isImm(Addr))
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return false;
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// it is [reg]
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assert(Addr.getValueType().isSimple() && "Type must be simple");
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, Addr.getValueType().getSimpleVT());
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return true;
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}
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if (Addr.getNumOperands() < 2)
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return false;
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// let SelectADDRii handle the [imm+imm] case
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if (isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1)))
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return false;
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// try [reg+imm] and [imm+reg]
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for (int i = 0; i < 2; i ++)
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if (SelectImm(Addr.getOperand(1-i), Offset)) {
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Base = Addr.getOperand(i);
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return true;
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}
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// neither [reg+imm] nor [imm+reg]
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return false;
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}
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bool PTXDAGToDAGISel::isImm(const SDValue &operand) {
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return ConstantSDNode::classof(operand.getNode());
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}
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@ -50,7 +50,9 @@ def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">;
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def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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const SDValue &MemOp = N->getOperand(1);
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if ((MemOp.getOpcode() != ISD::FrameIndex) &&
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(Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::GLOBAL;
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return false;
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@ -66,12 +68,8 @@ def load_constant : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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}]>;
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def load_local : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<LoadSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::LOCAL;
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return false;
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const SDValue &MemOp = N->getOperand(1);
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return MemOp.getOpcode() == ISD::FrameIndex;
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}]>;
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def load_parameter : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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@ -96,7 +94,9 @@ def store_global
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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const SDValue &MemOp = N->getOperand(2);
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if ((MemOp.getOpcode() != ISD::FrameIndex) &&
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(Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::GLOBAL;
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return false;
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@ -104,12 +104,8 @@ def store_global
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def store_local
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: PatFrag<(ops node:$d, node:$ptr), (store node:$d, node:$ptr), [{
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const Value *Src;
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const PointerType *PT;
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if ((Src = cast<StoreSDNode>(N)->getSrcValue()) &&
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(PT = dyn_cast<PointerType>(Src->getType())))
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return PT->getAddressSpace() == PTX::LOCAL;
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return false;
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const SDValue &MemOp = N->getOperand(2);
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return MemOp.getOpcode() == ISD::FrameIndex;
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}]>;
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def store_parameter
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@ -133,12 +129,14 @@ def store_shared
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}]>;
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// Addressing modes.
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def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
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def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
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def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
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def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
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def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
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def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
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def ADDRrr32 : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
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def ADDRrr64 : ComplexPattern<i64, 2, "SelectADDRrr", [], []>;
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def ADDRri32 : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
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def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri", [], []>;
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def ADDRii32 : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
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def ADDRii64 : ComplexPattern<i64, 2, "SelectADDRii", [], []>;
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def ADDRlocal32 : ComplexPattern<i32, 2, "SelectADDRlocal", [], []>;
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def ADDRlocal64 : ComplexPattern<i64, 2, "SelectADDRlocal", [], []>;
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// Address operands
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def MEMri32 : Operand<i32> {
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@ -903,7 +901,7 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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// Loads
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defm LDg : PTX_LD_ALL<"ld.global", load_global>;
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defm LDc : PTX_LD_ALL<"ld.const", load_constant>;
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defm LDl : PTX_LD_ALL<"ld.local", load_local>;
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//defm LDl : PTX_LD_ALL<"ld.local", load_local>;
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defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
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// These instructions are used to load/store from the .param space for
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@ -949,11 +947,101 @@ let hasSideEffects = 1 in {
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[(PTXstoreparam timm:$d, RegF64:$a)]>;
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}
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/*
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def ri64 : InstPTX<(outs RC:$d),
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(ins MEMri64:$a),
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!strconcat(opstr, !strconcat(typestr, "\t$d, [$a]")),
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[(set RC:$d, (pat_load ADDRri64:$a))]>,
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Requires<[Use64BitAddresses]>;
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def ri64 : InstPTX<(outs),
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(ins RC:$d, MEMri64:$a),
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!strconcat(opstr, !strconcat(typestr, "\t[$a], $d")),
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[(pat_store RC:$d, ADDRri64:$a)]>,
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Requires<[Use64BitAddresses]>;
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*/
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let hasSideEffects = 1 in {
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def LDLOCALpiPred : InstPTX<(outs RegPred:$d), (ins MEMri32:$a),
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"ld.local.pred\t$d, [__local_$a]",
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[(set RegPred:$d, (load_local ADDRlocal32:$a))]>;
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def LDLOCALpiU16 : InstPTX<(outs RegI16:$d), (ins MEMri32:$a),
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"ld.local.u16\t$d, [__local_$a]",
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[(set RegI16:$d, (load_local ADDRlocal32:$a))]>;
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def LDLOCALpiU32 : InstPTX<(outs RegI32:$d), (ins MEMri32:$a),
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"ld.local.u32\t$d, [__local_$a]",
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[(set RegI32:$d, (load_local ADDRlocal32:$a))]>;
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def LDLOCALpiU64 : InstPTX<(outs RegI64:$d), (ins MEMri32:$a),
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"ld.local.u64\t$d, [__local_$a]",
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[(set RegI64:$d, (load_local ADDRlocal32:$a))]>;
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def LDLOCALpiF32 : InstPTX<(outs RegF32:$d), (ins MEMri32:$a),
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"ld.local.f32\t$d, [__local_$a]",
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[(set RegF32:$d, (load_local ADDRlocal32:$a))]>;
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def LDLOCALpiF64 : InstPTX<(outs RegF64:$d), (ins MEMri32:$a),
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"ld.local.f64\t$d, [__local_$a]",
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[(set RegF64:$d, (load_local ADDRlocal32:$a))]>;
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def STLOCALpiPred : InstPTX<(outs), (ins RegPred:$d, MEMri32:$a),
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"st.local.pred\t[__local_$a], $d",
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[(store_local RegPred:$d, ADDRlocal32:$a)]>;
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def STLOCALpiU16 : InstPTX<(outs), (ins RegI16:$d, MEMri32:$a),
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"st.local.u16\t[__local_$a], $d",
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[(store_local RegI16:$d, ADDRlocal32:$a)]>;
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def STLOCALpiU32 : InstPTX<(outs), (ins RegI32:$d, MEMri32:$a),
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"st.local.u32\t[__local_$a], $d",
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[(store_local RegI32:$d, ADDRlocal32:$a)]>;
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def STLOCALpiU64 : InstPTX<(outs), (ins RegI64:$d, MEMri32:$a),
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"st.local.u64\t[__local_$a], $d",
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[(store_local RegI64:$d, ADDRlocal32:$a)]>;
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def STLOCALpiF32 : InstPTX<(outs), (ins RegF32:$d, MEMri32:$a),
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"st.local.f32\t[__local_$a], $d",
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[(store_local RegF32:$d, ADDRlocal32:$a)]>;
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def STLOCALpiF64 : InstPTX<(outs), (ins RegF64:$d, MEMri32:$a),
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"st.local.f64\t[__local_$a], $d",
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[(store_local RegF64:$d, ADDRlocal32:$a)]>;
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/*def LDLOCALpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
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"ld.param.u16\t$d, [$a]",
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[(set RegI16:$d, (PTXloadparam timm:$a))]>;
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def LDLOCALpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
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"ld.param.u32\t$d, [$a]",
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[(set RegI32:$d, (PTXloadparam timm:$a))]>;
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def LDLOCALpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a),
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"ld.param.u64\t$d, [$a]",
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[(set RegI64:$d, (PTXloadparam timm:$a))]>;
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def LDLOCALpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
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"ld.param.f32\t$d, [$a]",
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[(set RegF32:$d, (PTXloadparam timm:$a))]>;
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def LDLOCALpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
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"ld.param.f64\t$d, [$a]",
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[(set RegF64:$d, (PTXloadparam timm:$a))]>;
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def STLOCALpiPred : InstPTX<(outs), (ins MEMpi:$d, RegPred:$a),
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"st.param.pred\t[$d], $a",
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[(PTXstoreparam timm:$d, RegPred:$a)]>;
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def STLOCALpiU16 : InstPTX<(outs), (ins MEMpi:$d, RegI16:$a),
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"st.param.u16\t[$d], $a",
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[(PTXstoreparam timm:$d, RegI16:$a)]>;
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def STLOCALpiU32 : InstPTX<(outs), (ins MEMpi:$d, RegI32:$a),
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"st.param.u32\t[$d], $a",
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[(PTXstoreparam timm:$d, RegI32:$a)]>;
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def STLOCALpiU64 : InstPTX<(outs), (ins MEMpi:$d, RegI64:$a),
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"st.param.u64\t[$d], $a",
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[(PTXstoreparam timm:$d, RegI64:$a)]>;
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def STLOCALpiF32 : InstPTX<(outs), (ins MEMpi:$d, RegF32:$a),
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"st.param.f32\t[$d], $a",
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[(PTXstoreparam timm:$d, RegF32:$a)]>;
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def STLOCALpiF64 : InstPTX<(outs), (ins MEMpi:$d, RegF64:$a),
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"st.param.f64\t[$d], $a",
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[(PTXstoreparam timm:$d, RegF64:$a)]>;*/
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}
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// Stores
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defm STg : PTX_ST_ALL<"st.global", store_global>;
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defm STl : PTX_ST_ALL<"st.local", store_local>;
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//defm STl : PTX_ST_ALL<"st.local", store_local>;
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defm STs : PTX_ST_ALL<"st.shared", store_shared>;
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// defm STp : PTX_ST_ALL<"st.param", store_parameter>;
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// defm LDp : PTX_LD_ALL<"ld.param", load_parameter>;
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// TODO: Do something with st.param if/when it is needed.
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@ -1199,6 +1287,11 @@ def WRITEPARAMI64 : InstPTX<(outs), (ins RegI64:$a), "//w", []>;
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def WRITEPARAMF32 : InstPTX<(outs), (ins RegF32:$a), "//w", []>;
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def WRITEPARAMF64 : InstPTX<(outs), (ins RegF64:$a), "//w", []>;
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///===- Stack Variable Loads/Stores ---------------------------------------===//
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def LOAD_LOCAL_F32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
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"ld.local.f32\t$d, [%a]", []>;
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// Call handling
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// def ADJCALLSTACKUP :
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// InstPTX<(outs), (ins i32imm:$amt1, i32imm:$amt2), "",
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@ -14,6 +14,9 @@
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#include "PTX.h"
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#include "PTXRegisterInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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@ -23,16 +26,21 @@
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using namespace llvm;
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PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
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const TargetInstrInfo &TII)
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const TargetInstrInfo &tii)
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// PTX does not have a return address register.
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: PTXGenRegisterInfo(0) {
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: PTXGenRegisterInfo(0), TII(tii) {
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}
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void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj,
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RegScavenger *RS) const {
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unsigned Index;
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MachineInstr& MI = *II;
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MachineInstr &MI = *II;
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//MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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//MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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//unsigned Reg = MRI.createVirtualRegister(PTX::RegF32RegisterClass);
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Index = 0;
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while (!MI.getOperand(Index).isFI()) {
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@ -47,6 +55,15 @@ void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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DEBUG(dbgs() << "- SPAdj: " << SPAdj << "\n");
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DEBUG(dbgs() << "- FrameIndex: " << FrameIndex << "\n");
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//MachineInstr* MI2 = BuildMI(MBB, II, dl, TII.get(PTX::LOAD_LOCAL_F32))
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//.addReg(Reg, RegState::Define).addImm(FrameIndex);
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//if (MI2->findFirstPredOperandIdx() == -1) {
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// MI2->addOperand(MachineOperand::CreateReg(PTX::NoRegister, /*IsDef=*/false));
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// MI2->addOperand(MachineOperand::CreateImm(PTX::PRED_NORMAL));
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//}
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//MI2->dump();
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// This frame index is post stack slot re-use assignments
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MI.getOperand(Index).ChangeToImmediate(FrameIndex);
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//MI.getOperand(Index).ChangeToRegister(Reg, false);
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MI.getOperand(Index).ChangeToImmediate(0);
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}
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@ -25,8 +25,12 @@ class PTXTargetMachine;
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class MachineFunction;
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struct PTXRegisterInfo : public PTXGenRegisterInfo {
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private:
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const TargetInstrInfo &TII;
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public:
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PTXRegisterInfo(PTXTargetMachine &TM,
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const TargetInstrInfo &TII);
|
||||
const TargetInstrInfo &tii);
|
||||
|
||||
virtual const unsigned
|
||||
*getCalleeSavedRegs(const MachineFunction *MF = 0) const {
|
||||
|
||||
@ -118,7 +118,7 @@ bool PTXTargetMachine::addInstSelector(PassManagerBase &PM,
|
||||
bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM,
|
||||
CodeGenOpt::Level OptLevel) {
|
||||
// PTXMFInfoExtract must after register allocation!
|
||||
PM.add(createPTXMFInfoExtract(*this, OptLevel));
|
||||
//PM.add(createPTXMFInfoExtract(*this, OptLevel));
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -365,5 +365,7 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
|
||||
if (addPreEmitPass(PM, OptLevel))
|
||||
printNoVerify(PM, "After PreEmit passes");
|
||||
|
||||
PM.add(createPTXMFInfoExtract(*this, OptLevel));
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user