[llvm-exegesis] InMemoryAssembler: handle return-less targets (e.g. arm).

Summary: Arm does not have a ret code per se.

Reviewers: gchatelet

Subscribers: mgorny, javed.absar, kristof.beyls, tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D45672

llvm-svn: 332331
This commit is contained in:
Clement Courbet 2018-05-15 07:40:21 +00:00
parent 72eeaf5ee6
commit e80abfe602
5 changed files with 114 additions and 5 deletions

View File

@ -19,6 +19,7 @@ llvm_map_components_to_libnames(libs
CodeGen
Core
ExecutionEngine
GlobalISel
MC
MCJIT
Object

View File

@ -10,6 +10,8 @@
#include "InMemoryAssembler.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@ -139,9 +141,15 @@ static void fillMachineFunction(llvm::MachineFunction &MF,
}
}
}
// Adding the Return Opcode.
// Insert the return code.
const llvm::TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
llvm::BuildMI(MBB, DL, TII->get(TII->getReturnOpcode()));
if (TII->getReturnOpcode() < TII->getNumOpcodes()) {
llvm::BuildMI(MBB, DL, TII->get(TII->getReturnOpcode()));
} else {
llvm::MachineIRBuilder MIB(MF);
MIB.setMBB(*MBB);
MF.getSubtarget().getCallLowering()->lowerReturn(MIB, nullptr, 0);
}
}
namespace {

View File

@ -0,0 +1,20 @@
include_directories(
${LLVM_MAIN_SRC_DIR}/lib/Target/ARM
${LLVM_BINARY_DIR}/lib/Target/ARM
${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
)
set(LLVM_LINK_COMPONENTS
MC
MCParser
Object
Support
Symbolize
ARM
)
add_llvm_unittest(LLVMExegesisARMTests
InMemoryAssemblerTest.cpp
)
target_link_libraries(LLVMExegesisARMTests PRIVATE LLVMExegesis)

View File

@ -0,0 +1,79 @@
//===-- InMemoryAssemblerTest.cpp -------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "InMemoryAssembler.h"
#include "ARMInstrInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/Support/Host.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
#include <memory>
namespace exegesis {
namespace {
using llvm::MCInstBuilder;
using testing::ElementsAre;
class MachineFunctionGeneratorTest : public ::testing::Test {
protected:
MachineFunctionGeneratorTest()
: TT("armv7-none-linux-gnueabi"), CpuName("") {}
static void SetUpTestCase() {
LLVMInitializeARMTargetInfo();
LLVMInitializeARMTargetMC();
LLVMInitializeARMTarget();
LLVMInitializeARMAsmPrinter();
}
std::unique_ptr<llvm::LLVMTargetMachine> createTargetMachine() {
std::string Error;
const llvm::Target *TheTarget =
llvm::TargetRegistry::lookupTarget(TT, Error);
assert(TheTarget);
const llvm::TargetOptions Options;
return std::unique_ptr<llvm::LLVMTargetMachine>(
static_cast<llvm::LLVMTargetMachine *>(TheTarget->createTargetMachine(
TT, CpuName, "", Options, llvm::Reloc::Model::Static)));
}
private:
const std::string TT;
const std::string CpuName;
};
TEST_F(MachineFunctionGeneratorTest, JitFunction) {
JitFunctionContext Context(createTargetMachine());
JitFunction Function(std::move(Context), {});
ASSERT_THAT(Function.getFunctionBytes().str(),
ElementsAre(0x1e, 0xff, 0x2f, 0xe1));
}
TEST_F(MachineFunctionGeneratorTest, JitFunctionADDrr) {
JitFunctionContext Context(createTargetMachine());
JitFunction Function(std::move(Context), {MCInstBuilder(llvm::ARM::ADDrr)
.addReg(llvm::ARM::R0)
.addReg(llvm::ARM::R0)
.addReg(llvm::ARM::R0)
.addImm(llvm::ARMCC::AL)
.addReg(0)
.addReg(0)});
ASSERT_THAT(Function.getFunctionBytes().str(),
ElementsAre(0x00, 0x00, 0x80, 0xe0, 0x1e, 0xff, 0x2f, 0xe1));
}
} // namespace
} // namespace exegesis

View File

@ -23,7 +23,8 @@ if(LLVM_ENABLE_LIBPFM AND HAVE_LIBPFM)
endif()
if(LLVM_TARGETS_TO_BUILD MATCHES "X86")
add_subdirectory(
X86
)
add_subdirectory(X86)
endif()
if(LLVM_TARGETS_TO_BUILD MATCHES "ARM")
add_subdirectory(ARM)
endif()