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Floating point loads/stores act on memory operands. Rename them to

Browse Source 
denote this fact.

llvm-svn: 11971
This commit is contained in:
Alkis Evlogimenos 2004-02-28 23:42:35 +00:00
parent 1d71a15be9
commit e8dac99a43
5 changed files with 44 additions and 44 deletions
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14
lib/Target/X86/FloatingPoint.cpp
View File

@ -321,13 +321,13 @@ static const TableEntry PopTable[] = {
{ X86::FDIVRrST0, X86::FDIVRPrST0 }, { X86::FDIVRrST0, X86::FDIVRPrST0 },
{ X86::FDIVrST0 , X86::FDIVPrST0 }, { X86::FDIVrST0 , X86::FDIVPrST0 },
{ X86::FISTr16 , X86::FISTPr16 }, { X86::FISTm16 , X86::FISTPm16 },
{ X86::FISTr32 , X86::FISTPr32 }, { X86::FISTm32 , X86::FISTPm32 },
{ X86::FMULrST0 , X86::FMULPrST0 }, { X86::FMULrST0 , X86::FMULPrST0 },
{ X86::FSTr32 , X86::FSTPr32 }, { X86::FSTm32 , X86::FSTPm32 },
{ X86::FSTr64 , X86::FSTPr64 }, { X86::FSTm64 , X86::FSTPm64 },
{ X86::FSTrr , X86::FSTPrr }, { X86::FSTrr , X86::FSTPrr },
{ X86::FSUBRrST0, X86::FSUBRPrST0 }, { X86::FSUBRrST0, X86::FSUBRPrST0 },
@ -403,15 +403,15 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
// on the stack instead of moving it. This ensure that popping the value is // on the stack instead of moving it. This ensure that popping the value is
// always ok. // always ok.
// //
if ((MI->getOpcode() == X86::FSTPr80 || if ((MI->getOpcode() == X86::FSTPm80 ||
MI->getOpcode() == X86::FISTPr64) && !KillsSrc) { MI->getOpcode() == X86::FISTPm64) && !KillsSrc) {
duplicateToTop(Reg, 7 /*temp register*/, I); duplicateToTop(Reg, 7 /*temp register*/, I);
} else { } else {
moveToTop(Reg, I); // Move to the top of the stack... moveToTop(Reg, I); // Move to the top of the stack...
} }
MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand
if (MI->getOpcode() == X86::FSTPr80 || MI->getOpcode() == X86::FISTPr64) { if (MI->getOpcode() == X86::FSTPm80 || MI->getOpcode() == X86::FISTPm64) {
assert(StackTop > 0 && "Stack empty??"); assert(StackTop > 0 && "Stack empty??");
--StackTop; --StackTop;
} else if (KillsSrc) { // Last use of operand? } else if (KillsSrc) { // Last use of operand?

30
lib/Target/X86/InstSelectSimple.cpp
View File

@ -480,7 +480,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
const Type *Ty = CFP->getType(); const Type *Ty = CFP->getType();
assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!"); assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDr32 : X86::FLDr64; unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLDm32 : X86::FLDm64;
addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI); addConstantPoolReference(BMI(MBB, IP, LoadOpcode, 4, R), CPI);
} }
@ -536,10 +536,10 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
case cFP: case cFP:
unsigned Opcode; unsigned Opcode;
if (I->getType() == Type::FloatTy) { if (I->getType() == Type::FloatTy) {
Opcode = X86::FLDr32; Opcode = X86::FLDm32;
FI = MFI->CreateFixedObject(4, ArgOffset); FI = MFI->CreateFixedObject(4, ArgOffset);
} else { } else {
Opcode = X86::FLDr64; Opcode = X86::FLDm64;
FI = MFI->CreateFixedObject(8, ArgOffset); FI = MFI->CreateFixedObject(8, ArgOffset);
ArgOffset += 4; // doubles require 4 additional bytes ArgOffset += 4; // doubles require 4 additional bytes
} }
@ -1140,11 +1140,11 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
case cFP: case cFP:
if (Args[i].Ty == Type::FloatTy) { if (Args[i].Ty == Type::FloatTy) {
addRegOffset(BuildMI(BB, X86::FSTr32, 5), addRegOffset(BuildMI(BB, X86::FSTm32, 5),
X86::ESP, ArgOffset).addReg(ArgReg); X86::ESP, ArgOffset).addReg(ArgReg);
} else { } else {
assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!"); assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
addRegOffset(BuildMI(BB, X86::FSTr64, 5), addRegOffset(BuildMI(BB, X86::FSTm64, 5),
X86::ESP, ArgOffset).addReg(ArgReg); X86::ESP, ArgOffset).addReg(ArgReg);
ArgOffset += 4; // 8 byte entry, not 4. ArgOffset += 4; // 8 byte entry, not 4.
} }
@ -1929,10 +1929,10 @@ void ISel::visitLoadInst(LoadInst &I) {
} }
static const unsigned Opcodes[] = { static const unsigned Opcodes[] = {
X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDr32 X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDm32
}; };
unsigned Opcode = Opcodes[Class]; unsigned Opcode = Opcodes[Class];
if (I.getType() == Type::DoubleTy) Opcode = X86::FLDr64; if (I.getType() == Type::DoubleTy) Opcode = X86::FLDm64;
addFullAddress(BuildMI(BB, Opcode, 4, DestReg), addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
BaseReg, Scale, IndexReg, Disp); BaseReg, Scale, IndexReg, Disp);
} }
@ -1991,10 +1991,10 @@ void ISel::visitStoreInst(StoreInst &I) {
} else { } else {
unsigned ValReg = getReg(I.getOperand(0)); unsigned ValReg = getReg(I.getOperand(0));
static const unsigned Opcodes[] = { static const unsigned Opcodes[] = {
X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTr32 X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTm32
}; };
unsigned Opcode = Opcodes[Class]; unsigned Opcode = Opcodes[Class];
if (ValTy == Type::DoubleTy) Opcode = X86::FSTr64; if (ValTy == Type::DoubleTy) Opcode = X86::FSTm64;
addFullAddress(BuildMI(BB, Opcode, 1+4), addFullAddress(BuildMI(BB, Opcode, 1+4),
BaseReg, Scale, IndexReg, Disp).addReg(ValReg); BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
} }
@ -2089,8 +2089,8 @@ void ISel::emitCastOperation(MachineBasicBlock *BB,
// reading it back. // reading it back.
unsigned FltAlign = TM.getTargetData().getFloatAlignment(); unsigned FltAlign = TM.getTargetData().getFloatAlignment();
int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign); int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
addFrameReference(BMI(BB, IP, X86::FSTr32, 5), FrameIdx).addReg(SrcReg); addFrameReference(BMI(BB, IP, X86::FSTm32, 5), FrameIdx).addReg(SrcReg);
addFrameReference(BMI(BB, IP, X86::FLDr32, 5, DestReg), FrameIdx); addFrameReference(BMI(BB, IP, X86::FLDm32, 5, DestReg), FrameIdx);
} }
} else if (SrcClass == cLong) { } else if (SrcClass == cLong) {
BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg); BMI(BB, IP, X86::MOVrr32, 1, DestReg).addReg(SrcReg);
@ -2209,7 +2209,7 @@ void ISel::emitCastOperation(MachineBasicBlock *BB,
} }
static const unsigned Op2[] = static const unsigned Op2[] =
{ 0/*byte*/, X86::FILDr16, X86::FILDr32, 0/*FP*/, X86::FILDr64 }; { 0/*byte*/, X86::FILDm16, X86::FILDm32, 0/*FP*/, X86::FILDm64 };
addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx); addFrameReference(BMI(BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
// We need special handling for unsigned 64-bit integer sources. If the // We need special handling for unsigned 64-bit integer sources. If the
@ -2237,7 +2237,7 @@ void ISel::emitCastOperation(MachineBasicBlock *BB,
// Load the constant for an add. FIXME: this could make an 'fadd' that // Load the constant for an add. FIXME: this could make an 'fadd' that
// reads directly from memory, but we don't support these yet. // reads directly from memory, but we don't support these yet.
unsigned ConstReg = makeAnotherReg(Type::DoubleTy); unsigned ConstReg = makeAnotherReg(Type::DoubleTy);
addDirectMem(BMI(BB, IP, X86::FLDr32, 4, ConstReg), Addr); addDirectMem(BMI(BB, IP, X86::FLDm32, 4, ConstReg), Addr);
BMI(BB, IP, X86::FpADD, 2, RealDestReg).addReg(ConstReg).addReg(DestReg); BMI(BB, IP, X86::FpADD, 2, RealDestReg).addReg(ConstReg).addReg(DestReg);
} }
@ -2289,7 +2289,7 @@ void ISel::emitCastOperation(MachineBasicBlock *BB,
F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData()); F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
static const unsigned Op1[] = static const unsigned Op1[] =
{ 0, X86::FISTr16, X86::FISTr32, 0, X86::FISTPr64 }; { 0, X86::FISTm16, X86::FISTm32, 0, X86::FISTPm64 };
addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg); addFrameReference(BMI(BB, IP, Op1[StoreClass], 5), FrameIdx).addReg(SrcReg);
if (DestClass == cLong) { if (DestClass == cLong) {
@ -2358,7 +2358,7 @@ void ISel::visitVAArgInst(VAArgInst &I) {
addRegOffset(BuildMI(BB, X86::MOVrm32, 4, DestReg+1), VAList, 4); addRegOffset(BuildMI(BB, X86::MOVrm32, 4, DestReg+1), VAList, 4);
break; break;
case Type::DoubleTyID: case Type::DoubleTyID:
addDirectMem(BuildMI(BB, X86::FLDr64, 4, DestReg), VAList); addDirectMem(BuildMI(BB, X86::FLDm64, 4, DestReg), VAList);
break; break;
} }
} }

8
lib/Target/X86/Printer.cpp
View File

@ -772,7 +772,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// is misassembled by gas in intel_syntax mode as its 32-bit // is misassembled by gas in intel_syntax mode as its 32-bit
// equivalent "fstp DWORD PTR [...]". Workaround: Output the raw // equivalent "fstp DWORD PTR [...]". Workaround: Output the raw
// opcode bytes instead of the instruction. // opcode bytes instead of the instruction.
if (MI->getOpcode() == X86::FSTPr80) { if (MI->getOpcode() == X86::FSTPm80) {
if ((MI->getOperand(0).getReg() == X86::ESP) if ((MI->getOperand(0).getReg() == X86::ESP)
&& (MI->getOperand(1).getImmedValue() == 1)) { && (MI->getOperand(1).getImmedValue() == 1)) {
if (Op3.isImmediate() && if (Op3.isImmediate() &&
@ -793,7 +793,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// misassembled by gas in intel_syntax mode as its 32-bit // misassembled by gas in intel_syntax mode as its 32-bit
// equivalent "fld DWORD PTR [...]". Workaround: Output the raw // equivalent "fld DWORD PTR [...]". Workaround: Output the raw
// opcode bytes instead of the instruction. // opcode bytes instead of the instruction.
if (MI->getOpcode() == X86::FLDr80 && if (MI->getOpcode() == X86::FLDm80 &&
MI->getOperand(0).getReg() == X86::ESP && MI->getOperand(0).getReg() == X86::ESP &&
MI->getOperand(1).getImmedValue() == 1) { MI->getOperand(1).getImmedValue() == 1) {
if (Op3.isImmediate() && Op3.getImmedValue() >= -128 && if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
@ -813,7 +813,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// 64 bit modes." libopcodes disassembles it as "fild DWORD PTR // 64 bit modes." libopcodes disassembles it as "fild DWORD PTR
// [...]", which is wrong. Workaround: Output the raw opcode bytes // [...]", which is wrong. Workaround: Output the raw opcode bytes
// instead of the instruction. // instead of the instruction.
if (MI->getOpcode() == X86::FILDr64 && if (MI->getOpcode() == X86::FILDm64 &&
MI->getOperand(0).getReg() == X86::ESP && MI->getOperand(0).getReg() == X86::ESP &&
MI->getOperand(1).getImmedValue() == 1) { MI->getOperand(1).getImmedValue() == 1) {
if (Op3.isImmediate() && Op3.getImmedValue() >= -128 && if (Op3.isImmediate() && Op3.getImmedValue() >= -128 &&
@ -834,7 +834,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// "fistpll DWORD PTR [...]", which is wrong. Workaround: Output // "fistpll DWORD PTR [...]", which is wrong. Workaround: Output
// "fistpll DWORD PTR " instead, which is what libopcodes is // "fistpll DWORD PTR " instead, which is what libopcodes is
// expecting to see. // expecting to see.
if (MI->getOpcode() == X86::FISTPr64) { if (MI->getOpcode() == X86::FISTPm64) {
O << "fistpll DWORD PTR "; O << "fistpll DWORD PTR ";
printMemReference(MI, 0); printMemReference(MI, 0);
if (MI->getNumOperands() == 5) { if (MI->getNumOperands() == 5) {

32
lib/Target/X86/X86InstrInfo.td
View File

@ -639,26 +639,26 @@ def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR
// Floating point loads & stores... // Floating point loads & stores...
def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i)) def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
def FLDr32 : FPIm32 <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float def FLDm32 : FPIm32 <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
def FLDr64 : FPIm64 <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double def FLDm64 : FPIm64 <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double
def FLDr80 : FPIm80 <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended def FLDm80 : FPIm80 <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended
def FILDr16 : FPIm16 <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load signed short def FILDm16 : FPIm16 <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load signed short
def FILDr32 : FPIm32 <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int def FILDm32 : FPIm32 <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int
def FILDr64 : FPIm64 <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long def FILDm64 : FPIm64 <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long
def FSTrr : FPI <"fst" , 0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0) def FSTrr : FPI <"fst" , 0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0)
def FSTPrr : FPI <"fstp", 0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop def FSTPrr : FPI <"fstp", 0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop
def FSTr32 : FPIm32 <"fst" , 0xD9, MRM2m , OneArgFP>; // store float def FSTm32 : FPIm32 <"fst" , 0xD9, MRM2m , OneArgFP>; // store float
def FSTr64 : FPIm64 <"fst" , 0xDD, MRM2m , OneArgFP>; // store double def FSTm64 : FPIm64 <"fst" , 0xDD, MRM2m , OneArgFP>; // store double
def FSTPr32 : FPIm32 <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop def FSTPm32 : FPIm32 <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop
def FSTPr64 : FPIm64 <"fstp", 0xDD, MRM3m , OneArgFP>; // store double, pop def FSTPm64 : FPIm64 <"fstp", 0xDD, MRM3m , OneArgFP>; // store double, pop
def FSTPr80 : FPIm80 <"fstp", 0xDB, MRM7m , OneArgFP>; // store extended, pop def FSTPm80 : FPIm80 <"fstp", 0xDB, MRM7m , OneArgFP>; // store extended, pop
def FISTr16 : FPIm16 <"fist", 0xDF, MRM2m , OneArgFP>; // store signed short def FISTm16 : FPIm16 <"fist", 0xDF, MRM2m , OneArgFP>; // store signed short
def FISTr32 : FPIm32 <"fist", 0xDB, MRM2m , OneArgFP>; // store signed int def FISTm32 : FPIm32 <"fist", 0xDB, MRM2m , OneArgFP>; // store signed int
def FISTPr16 : FPIm16 <"fistp", 0xDF, MRM3m , NotFP >; // store signed short, pop def FISTPm16 : FPIm16 <"fistp", 0xDF, MRM3m , NotFP >; // store signed short, pop
def FISTPr32 : FPIm32 <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop def FISTPm32 : FPIm32 <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop
def FISTPr64 : FPIm64 <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop def FISTPm64 : FPIm64 <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop
def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0) def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0)

4
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -59,7 +59,7 @@ int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, int FrameIdx, unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
static const unsigned Opcode[] = static const unsigned Opcode[] =
{ X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTPr80 }; { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTPm80 };
MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5), MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
FrameIdx).addReg(SrcReg); FrameIdx).addReg(SrcReg);
MBB.insert(MI, I); MBB.insert(MI, I);
@ -71,7 +71,7 @@ int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned DestReg, int FrameIdx, unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const{ const TargetRegisterClass *RC) const{
static const unsigned Opcode[] = static const unsigned Opcode[] =
{ X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDr80 }; { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDm80 };
unsigned OC = Opcode[getIdx(RC)]; unsigned OC = Opcode[getIdx(RC)];
MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx)); MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
return 1; return 1;