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[AVX-512] Remove an AddedComplexity that was prioritizing basic vzmovl patterns over more complex ones that produce better code.

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llvm-svn: 278593
This commit is contained in:
Craig Topper 2016-08-13 05:43:20 +00:00
parent d1202028d7
commit e938340bf9
2 changed files with 7 additions and 13 deletions
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2
lib/Target/X86/X86InstrAVX512.td
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@ -3162,6 +3162,7 @@ let Predicates = [HasAVX512] in {
(VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>; (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))), def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
(VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>; (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
}
// Move low f32 and clear high bits. // Move low f32 and clear high bits.
def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))), def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
@ -3172,7 +3173,6 @@ let Predicates = [HasAVX512] in {
(SUBREG_TO_REG (i32 0), (SUBREG_TO_REG (i32 0),
(VMOVSSZrr (v4i32 (V_SET0)), (VMOVSSZrr (v4i32 (V_SET0)),
(EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>; (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
}
def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))), def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))),
(SUBREG_TO_REG (i32 0), (SUBREG_TO_REG (i32 0),
(VMOVSSZrr (v4f32 (V_SET0)), (VMOVSSZrr (v4f32 (V_SET0)),

18
test/CodeGen/X86/vector-shuffle-512-v64.ll
View File

@ -93,20 +93,16 @@ define <64 x i8> @shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<64 x i8> %a) {
; AVX512F: # BB#0: ; AVX512F: # BB#0:
; AVX512F-NEXT: movl $255, %eax ; AVX512F-NEXT: movl $255, %eax
; AVX512F-NEXT: vmovd %eax, %xmm1 ; AVX512F-NEXT: vmovd %eax, %xmm1
; AVX512F-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX512F-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3] ; AVX512F-NEXT: vpxor %ymm1, %ymm1, %ymm1
; AVX512F-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: vxorps %ymm1, %ymm1, %ymm1
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512BW-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: ; AVX512BW-LABEL: shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz:
; AVX512BW: # BB#0: ; AVX512BW: # BB#0:
; AVX512BW-NEXT: movl $255, %eax ; AVX512BW-NEXT: movl $255, %eax
; AVX512BW-NEXT: vmovd %eax, %xmm1 ; AVX512BW-NEXT: vmovd %eax, %xmm1
; AVX512BW-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX512BW-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3] ; AVX512BW-NEXT: vpxor %ymm1, %ymm1, %ymm1
; AVX512BW-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX512BW-NEXT: vxorps %ymm1, %ymm1, %ymm1
; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
@ -114,10 +110,8 @@ define <64 x i8> @shuffle_v64i8_0zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz(<64 x i8> %a) {
; AVX512DQ: # BB#0: ; AVX512DQ: # BB#0:
; AVX512DQ-NEXT: movl $255, %eax ; AVX512DQ-NEXT: movl $255, %eax
; AVX512DQ-NEXT: vmovd %eax, %xmm1 ; AVX512DQ-NEXT: vmovd %eax, %xmm1
; AVX512DQ-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX512DQ-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX512DQ-NEXT: vmovss {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3] ; AVX512DQ-NEXT: vpxor %ymm1, %ymm1, %ymm1
; AVX512DQ-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX512DQ-NEXT: vxorps %ymm1, %ymm1, %ymm1
; AVX512DQ-NEXT: retq ; AVX512DQ-NEXT: retq
%shuffle = shufflevector <64 x i8> %a, <64 x i8> zeroinitializer, <64 x i32> <i32 0, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64> %shuffle = shufflevector <64 x i8> %a, <64 x i8> zeroinitializer, <64 x i32> <i32 0, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>
ret <64 x i8> %shuffle ret <64 x i8> %shuffle