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[Hexagon] Adding tfrih/l instructions.

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llvm-svn: 223506
This commit is contained in:
Colin LeMahieu 2014-12-05 20:07:19 +00:00
parent 38a80209d6
commit ea4694aa6c
2 changed files with 26 additions and 0 deletions
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22
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -391,6 +391,28 @@ multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
[]>;
}
let hasSideEffects = 0, hasNewValue = 1 in
class T_tfr16<bit isHi>
: ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
"$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
[], "$src1 = $Rx" > {
bits<5> Rx;
bits<16> u16;
let IClass = 0b0111;
let Inst{27-26} = 0b00;
let Inst{25-24} = !if(isHi, 0b10, 0b01);
let Inst{23-22} = u16{15-14};
let Inst{21} = 0b1;
let Inst{20-16} = Rx;
let Inst{13-0} = u16{13-0};
}
let isCodeGenOnly = 0 in {
def A2_tfril: T_tfr16<0>;
def A2_tfrih: T_tfr16<1>;
}
multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let isPredicatedFalse = PredNot in {
defm _c#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 0>;

4
test/MC/Disassembler/Hexagon/alu32_alu.txt
View File

@ -16,5 +16,9 @@
# CHECK: r17 = sub(r31, r21)
0x11 0xc0 0xbf 0x70
# CHECK: r17 = sxtb(r31)
0x15 0xc0 0x31 0x72
# CHECK: r17.h = #21
0x15 0xc0 0x31 0x71
# CHECK: r17.l = #21
0x11 0xc0 0xd5 0x70
# CHECK: r17 = zxth(r21)