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Disable the Thumb no-return call optimization:

Browse Source 
mov lr, pc
b.w _foo

The "mov" instruction doesn't set bit zero to one, it's putting incorrect
value in lr. It messes up backtraces.

rdar://12663632

llvm-svn: 167657
This commit is contained in:
Evan Cheng 2012-11-10 02:09:05 +00:00
parent f424da6ff9
commit ebe241fb9d
5 changed files with 2 additions and 62 deletions
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25
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -1413,31 +1413,6 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
}
return;
}
case ARM::t2BMOVPCB_CALL: {
{
MCInst TmpInst;
TmpInst.setOpcode(ARM::tMOVr);
TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
// Add predicate operands.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
TmpInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(TmpInst);
}
{
MCInst TmpInst;
TmpInst.setOpcode(ARM::t2B);
const GlobalValue *GV = MI->getOperand(0).getGlobal();
MCSymbol *GVSym = Mang->getSymbol(GV);
const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
// Add predicate operands.
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
TmpInst.addOperand(MCOperand::CreateReg(0));
OutStreamer.EmitInstruction(TmpInst);
}
return;
}
case ARM::MOVi16_ga_pcrel:
case ARM::t2MOVi16_ga_pcrel: {
MCInst TmpInst;

10
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1599,18 +1599,12 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (Subtarget->isThumb()) {
if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
CallOpc = ARMISD::CALL_NOLINK;
else if (doesNotRet && isDirect && !isARMFunc &&
Subtarget->hasRAS() && !Subtarget->isThumb1Only() &&
// Emit regular call when code size is the priority
!HasMinSizeAttr)
// "mov lr, pc; b _foo" to avoid confusing the RSP
CallOpc = ARMISD::CALL_NOLINK;
else
CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
} else {
if (!isDirect && !Subtarget->hasV5TOps()) {
if (!isDirect && !Subtarget->hasV5TOps())
CallOpc = ARMISD::CALL_NOLINK;
} else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
// Emit regular call when code size is the priority
!HasMinSizeAttr)
// "mov lr, pc; b _foo" to avoid confusing the RSP

14
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3331,20 +3331,6 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
Requires<[IsThumb2, IsIOS]>;
}
let isCall = 1, Defs = [LR], Uses = [SP] in {
// mov lr, pc; b if callee is marked noreturn to avoid confusing the
// return stack predictor.
def t2BMOVPCB_CALL : tPseudoInst<(outs),
(ins t_bltarget:$func),
6, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
Requires<[IsThumb]>;
}
// Direct calls
def : T2Pat<(ARMcall_nolink texternalsym:$func),
(t2BMOVPCB_CALL texternalsym:$func)>,
Requires<[IsThumb]>;
// IT block
let Defs = [ITSTATE] in
def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),

7
test/CodeGen/ARM/call-noret-minsize.ll
View File

@ -1,6 +1,5 @@
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
; rdar://12348580
define void @t1() noreturn minsize nounwind ssp {
@ -10,9 +9,6 @@ entry:
; SWIFT: t1:
; SWIFT: bl _bar
; T2: t1:
; T2: blx _bar
tail call void @bar() noreturn nounwind
unreachable
}
@ -24,9 +20,6 @@ entry:
; SWIFT: t2:
; SWIFT: bl _t1
; T2: t2:
; T2: bl _t1
tail call void @t1() noreturn nounwind
unreachable
}

8
test/CodeGen/ARM/call-noret.ll
View File

@ -1,6 +1,5 @@
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
; rdar://8979299
define void @t1() noreturn nounwind ssp {
@ -12,9 +11,6 @@ entry:
; SWIFT: t1:
; SWIFT: mov lr, pc
; SWIFT: b _bar
; T2: t1:
; T2: blx _bar
tail call void @bar() noreturn nounwind
unreachable
}
@ -28,10 +24,6 @@ entry:
; SWIFT: t2:
; SWIFT: mov lr, pc
; SWIFT: b _t1
; T2: t2:
; T2: mov lr, pc
; T2: b.w _t1
tail call void @t1() noreturn nounwind
unreachable
}