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Use a SparseSet in LiveRegUnits.
Some clients may add block live ins and may track liveness over a large scope. This guarantees an efficient implementation in all cases with no memory allocation/deallocation, independent of the number of target registers. It could be slightly less convenient but is fine in the expected case. llvm-svn: 192622
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@ -17,9 +17,9 @@
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#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
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#define LLVM_CODEGEN_LIVEREGUNITS_H
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <cassert>
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namespace llvm {
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@ -29,17 +29,23 @@ class MachineInstr;
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/// A set of live register units with functions to track liveness when walking
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/// backward/forward through a basic block.
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class LiveRegUnits {
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SmallSet<unsigned, 32> LiveUnits;
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SparseSet<unsigned> LiveUnits;
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LiveRegUnits(const LiveRegUnits&) LLVM_DELETED_FUNCTION;
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LiveRegUnits &operator=(const LiveRegUnits&) LLVM_DELETED_FUNCTION;
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public:
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/// \brief Constructs a new empty LiveRegUnits set.
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LiveRegUnits() {}
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/// \brief Constructs a new LiveRegUnits set by copying @p Other.
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LiveRegUnits(const LiveRegUnits &Other)
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: LiveUnits(Other.LiveUnits) {
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void init(const TargetRegisterInfo *TRI) {
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LiveUnits.clear();
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LiveUnits.setUniverse(TRI->getNumRegs());
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}
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void clear() { LiveUnits.clear(); }
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bool empty() const { return LiveUnits.empty(); }
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/// \brief Adds a register to the set.
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void addReg(unsigned Reg, const MCRegisterInfo &MCRI) {
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for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
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@ -73,7 +79,7 @@ public:
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/// instruction(bundle): Remove killed-uses, add defs.
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void stepForward(const MachineInstr &MI, const MCRegisterInfo &MCRI);
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/// Adds all registers in the live-in list of block @p BB.
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/// \brief Adds all registers in the live-in list of block @p BB.
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void addLiveIns(const MachineBasicBlock &BB, const MCRegisterInfo &MCRI);
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};
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@ -162,6 +162,9 @@ namespace {
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const MachineBranchProbabilityInfo *MBPI;
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MachineRegisterInfo *MRI;
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LiveRegUnits Redefs;
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LiveRegUnits DontKill;
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bool PreRegAlloc;
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bool MadeChange;
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int FnNum;
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@ -202,12 +205,9 @@ namespace {
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void PredicateBlock(BBInfo &BBI,
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MachineBasicBlock::iterator E,
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SmallVectorImpl<MachineOperand> &Cond,
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LiveRegUnits &Redefs,
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SmallSet<unsigned, 4> *LaterRedefs = 0);
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void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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SmallVectorImpl<MachineOperand> &Cond,
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LiveRegUnits &Redefs,
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const LiveRegUnits *DontKill = 0,
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bool IgnoreBr = false);
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void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true);
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@ -1048,27 +1048,27 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
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// Initialize liveins to the first BB. These are potentiall redefined by
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// predicated instructions.
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LiveRegUnits Redefs;
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Redefs.init(TRI);
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Redefs.addLiveIns(*(CvtBBI->BB), *TRI);
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Redefs.addLiveIns(*(NextBBI->BB), *TRI);
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// Compute a set of registers which must not be killed by instructions in
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// BB1: This is everything live-in to BB2.
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LiveRegUnits DontKill;
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DontKill.init(TRI);
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DontKill.addLiveIns(*(NextBBI->BB), *TRI);
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if (CvtBBI->BB->pred_size() > 1) {
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BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
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// Copy instructions in the true block, predicate them, and add them to
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// the entry block.
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CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, &DontKill);
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CopyAndPredicateBlock(BBI, *CvtBBI, Cond);
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// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
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// explicitly remove CvtBBI as a successor.
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BBI.BB->removeSuccessor(CvtBBI->BB);
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} else {
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RemoveKills(CvtBBI->BB->begin(), CvtBBI->BB->end(), DontKill, *TRI);
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PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs);
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PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
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// Merge converted block into entry block.
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BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
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@ -1153,16 +1153,18 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
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// Initialize liveins to the first BB. These are potentially redefined by
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// predicated instructions.
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LiveRegUnits Redefs;
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Redefs.init(TRI);
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Redefs.addLiveIns(*(CvtBBI->BB), *TRI);
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Redefs.addLiveIns(*(NextBBI->BB), *TRI);
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DontKill.clear();
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bool HasEarlyExit = CvtBBI->FalseBB != NULL;
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if (CvtBBI->BB->pred_size() > 1) {
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BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
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// Copy instructions in the true block, predicate them, and add them to
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// the entry block.
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CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, 0, true);
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CopyAndPredicateBlock(BBI, *CvtBBI, Cond, true);
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// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
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// explicitly remove CvtBBI as a successor.
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@ -1170,7 +1172,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
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} else {
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// Predicate the 'true' block after removing its branch.
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CvtBBI->NonPredSize -= TII->RemoveBranch(*CvtBBI->BB);
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PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs);
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PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond);
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// Now merge the entry of the triangle with the true block.
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BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
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@ -1281,7 +1283,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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// Initialize liveins to the first BB. These are potentially redefined by
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// predicated instructions.
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LiveRegUnits Redefs;
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Redefs.init(TRI);
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Redefs.addLiveIns(*(BBI1->BB), *TRI);
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// Remove the duplicated instructions at the beginnings of both paths.
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@ -1312,7 +1314,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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// Compute a set of registers which must not be killed by instructions in BB1:
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// This is everything used+live in BB2 after the duplicated instructions. We
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// can compute this set by simulating liveness backwards from the end of BB2.
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LiveRegUnits DontKill;
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DontKill.init(TRI);
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for (MachineBasicBlock::reverse_iterator I = BBI2->BB->rbegin(),
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E = MachineBasicBlock::reverse_iterator(DI2); I != E; ++I) {
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DontKill.stepBackward(*I, *TRI);
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@ -1401,10 +1403,10 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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}
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// Predicate the 'true' block.
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PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, Redefs, &RedefsByFalse);
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PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, &RedefsByFalse);
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// Predicate the 'false' block.
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PredicateBlock(*BBI2, DI2, *Cond2, Redefs);
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PredicateBlock(*BBI2, DI2, *Cond2);
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// Merge the true block into the entry of the diamond.
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MergeBlocks(BBI, *BBI1, TailBB == 0);
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@ -1479,7 +1481,6 @@ static bool MaySpeculate(const MachineInstr *MI,
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void IfConverter::PredicateBlock(BBInfo &BBI,
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MachineBasicBlock::iterator E,
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SmallVectorImpl<MachineOperand> &Cond,
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LiveRegUnits &Redefs,
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SmallSet<unsigned, 4> *LaterRedefs) {
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bool AnyUnpred = false;
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bool MaySpec = LaterRedefs != 0;
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@ -1522,8 +1523,6 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
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/// the destination block. Skip end of block branches if IgnoreBr is true.
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void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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SmallVectorImpl<MachineOperand> &Cond,
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LiveRegUnits &Redefs,
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const LiveRegUnits *DontKill,
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bool IgnoreBr) {
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MachineFunction &MF = *ToBBI.BB->getParent();
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@ -1556,8 +1555,8 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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UpdatePredRedefs(MI, Redefs, TRI);
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// Some kill flags may not be correct anymore.
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if (DontKill != 0)
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RemoveKills(*MI, *DontKill, *TRI);
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if (!DontKill.empty())
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RemoveKills(*MI, DontKill, *TRI);
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}
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if (!IgnoreBr) {
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