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[llvm-exegeis] Computing Latency configuration upfront so we can generate many CodeTemplates at once.
Summary: LatencyGenerator now computes all possible mode of serial execution for an Instruction upfront and generates CodeTemplate for the ones that give the best results (e.g. no need to generate a two instructions snippet when repeating a single one would do). The next step is to generate even more configurations for cases (e.g. for XOR we should generate "XOR EAX, EAX, EAX" and "XOR EAX, EAX, EBX") Reviewers: courbet Reviewed By: courbet Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53320 llvm-svn: 344689
This commit is contained in:
Guillaume Chatelet
parent
7472803a23
commit
ee936f9a64
@ -65,4 +65,54 @@ llvm::MCInst InstructionTemplate::build() const {
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return Result;
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}
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bool isEnumValue(ExecutionMode Execution) {
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return llvm::isPowerOf2_32(static_cast<uint32_t>(Execution));
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}
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llvm::StringRef getName(ExecutionMode Bit) {
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assert(isEnumValue(Bit) && "Bit must be a power of two");
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switch (Bit) {
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case ExecutionMode::UNKNOWN:
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return "UNKNOWN";
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case ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS:
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return "ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS";
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case ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS:
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return "ALWAYS_SERIAL_TIED_REGS_ALIAS";
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case ExecutionMode::SERIAL_VIA_MEMORY_INSTR:
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return "SERIAL_VIA_MEMORY_INSTR";
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case ExecutionMode::SERIAL_VIA_EXPLICIT_REGS:
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return "SERIAL_VIA_EXPLICIT_REGS";
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case ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR:
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return "SERIAL_VIA_NON_MEMORY_INSTR";
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case ExecutionMode::ALWAYS_PARALLEL_MISSING_USE_OR_DEF:
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return "ALWAYS_PARALLEL_MISSING_USE_OR_DEF";
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case ExecutionMode::PARALLEL_VIA_EXPLICIT_REGS:
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return "PARALLEL_VIA_EXPLICIT_REGS";
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}
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llvm_unreachable("Missing enum case");
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}
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static const ExecutionMode kAllExecutionModeBits[] = {
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ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS,
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ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS,
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ExecutionMode::SERIAL_VIA_MEMORY_INSTR,
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ExecutionMode::SERIAL_VIA_EXPLICIT_REGS,
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ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR,
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ExecutionMode::ALWAYS_PARALLEL_MISSING_USE_OR_DEF,
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ExecutionMode::PARALLEL_VIA_EXPLICIT_REGS,
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};
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llvm::ArrayRef<ExecutionMode> getAllExecutionBits() {
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return kAllExecutionModeBits;
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}
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llvm::SmallVector<ExecutionMode, 4>
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getExecutionModeBits(ExecutionMode Execution) {
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llvm::SmallVector<ExecutionMode, 4> Result;
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for (const auto Bit : getAllExecutionBits())
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if ((Execution & Bit) == Bit)
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Result.push_back(Bit);
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return Result;
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}
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} // namespace exegesis
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@ -17,6 +17,7 @@
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#define LLVM_TOOLS_LLVM_EXEGESIS_CODETEMPLATE_H
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#include "MCInstrDescView.h"
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#include "llvm/ADT/BitmaskEnum.h"
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namespace exegesis {
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@ -45,9 +46,65 @@ struct InstructionTemplate {
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llvm::SmallVector<llvm::MCOperand, 4> VariableValues;
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};
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enum class ExecutionMode : uint8_t {
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UNKNOWN = 0U,
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// The instruction is always serial because implicit Use and Def alias.
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// e.g. AAA (alias via EFLAGS)
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ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS = 1u << 0,
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// The instruction is always serial because one Def is tied to a Use.
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// e.g. AND32ri (alias via tied GR32)
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ALWAYS_SERIAL_TIED_REGS_ALIAS = 1u << 1,
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// The execution can be made serial by inserting a second instruction that
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// clobbers/reads memory.
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// e.g. MOV8rm
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SERIAL_VIA_MEMORY_INSTR = 1u << 2,
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// The execution can be made serial by picking one Def that aliases with one
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// Use.
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// e.g. VXORPSrr XMM1, XMM1, XMM2
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SERIAL_VIA_EXPLICIT_REGS = 1u << 3,
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// The execution can be made serial by inserting a second instruction that
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// uses one of the Defs and defs one of the Uses.
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// e.g.
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// 1st instruction: MMX_PMOVMSKBrr ECX, MM7
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// 2nd instruction: MMX_MOVD64rr MM7, ECX
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// or instruction: MMX_MOVD64to64rr MM7, ECX
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// or instruction: MMX_PINSRWrr MM7, MM7, ECX, 1
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SERIAL_VIA_NON_MEMORY_INSTR = 1u << 4,
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// The execution is always parallel because the instruction is missing Use or
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// Def operands.
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ALWAYS_PARALLEL_MISSING_USE_OR_DEF = 1u << 5,
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// The execution can be made parallel by repeating the same instruction but
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// making sure that Defs of one instruction do not alias with Uses of the
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// second one.
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PARALLEL_VIA_EXPLICIT_REGS = 1u << 6,
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LLVM_MARK_AS_BITMASK_ENUM(/*Largest*/ PARALLEL_VIA_EXPLICIT_REGS)
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};
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// Returns whether Execution is one of the values defined in the enum above.
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bool isEnumValue(ExecutionMode Execution);
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// Returns a human readable string for the enum.
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llvm::StringRef getName(ExecutionMode Execution);
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// Returns a sequence of increasing powers of two corresponding to all the
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// Execution flags.
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llvm::ArrayRef<ExecutionMode> getAllExecutionBits();
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// Decomposes Execution into individual set bits.
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llvm::SmallVector<ExecutionMode, 4> getExecutionModeBits(ExecutionMode);
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LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE();
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// A CodeTemplate is a set of InstructionTemplates that may not be fully
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// specified (i.e. some variables are not yet set). This allows the
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// BenchmarkRunner to instantiate it many times with specific values to study
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// SnippetGenerator to instantiate it many times with specific values to study
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// their impact on instruction's performance.
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struct CodeTemplate {
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CodeTemplate() = default;
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@ -57,6 +114,7 @@ struct CodeTemplate {
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CodeTemplate(const CodeTemplate &) = delete;
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CodeTemplate &operator=(const CodeTemplate &) = delete;
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ExecutionMode Execution = ExecutionMode::UNKNOWN;
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// Some information about how this template has been created.
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std::string Info;
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// The list of the instructions for this template.
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@ -20,53 +20,148 @@
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namespace exegesis {
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LatencySnippetGenerator::~LatencySnippetGenerator() = default;
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struct ExecutionClass {
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ExecutionMode Mask;
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const char *Description;
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} static const kExecutionClasses[] = {
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{ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS |
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ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS,
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"Repeating a single implicitly serial instruction"},
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{ExecutionMode::SERIAL_VIA_EXPLICIT_REGS,
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"Repeating a single explicitly serial instruction"},
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{ExecutionMode::SERIAL_VIA_MEMORY_INSTR |
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ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR,
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"Repeating two instructions"},
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};
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llvm::Expected<std::vector<CodeTemplate>>
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generateTwoInstructionPrototypes(const LLVMState &State,
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const Instruction &Instr) {
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static constexpr size_t kMaxAliasingInstructions = 10;
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static std::vector<Instruction>
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computeAliasingInstructions(const LLVMState &State, const Instruction &Instr,
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size_t MaxAliasingInstructions) {
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// Randomly iterate the set of instructions.
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std::vector<unsigned> Opcodes;
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Opcodes.resize(State.getInstrInfo().getNumOpcodes());
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std::iota(Opcodes.begin(), Opcodes.end(), 0U);
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std::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
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std::vector<Instruction> AliasingInstructions;
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for (const unsigned OtherOpcode : Opcodes) {
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if (OtherOpcode == Instr.Description->Opcode)
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if (OtherOpcode == Instr.Description->getOpcode())
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continue;
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const Instruction OtherInstr(State, OtherOpcode);
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if (OtherInstr.hasMemoryOperands())
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continue;
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const AliasingConfigurations Forward(Instr, OtherInstr);
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const AliasingConfigurations Back(OtherInstr, Instr);
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if (Forward.empty() || Back.empty())
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continue;
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InstructionTemplate ThisIT(Instr);
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InstructionTemplate OtherIT(OtherInstr);
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if (!Forward.hasImplicitAliasing())
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setRandomAliasing(Forward, ThisIT, OtherIT);
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if (!Back.hasImplicitAliasing())
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setRandomAliasing(Back, OtherIT, ThisIT);
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CodeTemplate CT;
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CT.Info = llvm::formatv("creating cycle through {0}.",
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State.getInstrInfo().getName(OtherOpcode));
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CT.Instructions.push_back(std::move(ThisIT));
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CT.Instructions.push_back(std::move(OtherIT));
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return getSingleton(CT);
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if (Instr.hasAliasingRegistersThrough(OtherInstr))
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AliasingInstructions.push_back(std::move(OtherInstr));
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if (AliasingInstructions.size() >= MaxAliasingInstructions)
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break;
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}
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return llvm::make_error<BenchmarkFailure>(
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"Infeasible : Didn't find any scheme to make the instruction serial");
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return AliasingInstructions;
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}
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static ExecutionMode getExecutionModes(const Instruction &Instr) {
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ExecutionMode EM;
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if (Instr.hasAliasingImplicitRegisters())
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EM |= ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS;
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if (Instr.hasTiedRegisters())
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EM |= ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS;
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if (Instr.hasMemoryOperands())
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EM |= ExecutionMode::SERIAL_VIA_MEMORY_INSTR;
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else {
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if (Instr.hasAliasingRegisters())
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EM |= ExecutionMode::SERIAL_VIA_EXPLICIT_REGS;
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if (Instr.hasOneUseOrOneDef())
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EM |= ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR;
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}
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return EM;
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}
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static void appendCodeTemplates(const LLVMState &State,
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const Instruction &Instr,
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ExecutionMode ExecutionModeBit,
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llvm::StringRef ExecutionClassDescription,
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std::vector<CodeTemplate> &CodeTemplates) {
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assert(isEnumValue(ExecutionModeBit) && "Bit must be a power of two");
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switch (ExecutionModeBit) {
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case ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS:
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// Nothing to do, the instruction is always serial.
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LLVM_FALLTHROUGH;
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case ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS: {
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// Picking whatever value for the tied variable will make the instruction
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// serial.
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CodeTemplate CT;
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CT.Execution = ExecutionModeBit;
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CT.Info = ExecutionClassDescription;
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CT.Instructions.push_back(Instr);
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CodeTemplates.push_back(std::move(CT));
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return;
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}
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case ExecutionMode::SERIAL_VIA_MEMORY_INSTR: {
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// Select back-to-back memory instruction.
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// TODO: Implement me.
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return;
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}
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case ExecutionMode::SERIAL_VIA_EXPLICIT_REGS: {
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// Making the execution of this instruction serial by selecting one def
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// register to alias with one use register.
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const AliasingConfigurations SelfAliasing(Instr, Instr);
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assert(!SelfAliasing.empty() && !SelfAliasing.hasImplicitAliasing() &&
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"Instr must alias itself explicitly");
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InstructionTemplate IT(Instr);
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// This is a self aliasing instruction so defs and uses are from the same
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// instance, hence twice IT in the following call.
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setRandomAliasing(SelfAliasing, IT, IT);
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CodeTemplate CT;
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CT.Execution = ExecutionModeBit;
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CT.Info = ExecutionClassDescription;
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CT.Instructions.push_back(std::move(IT));
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CodeTemplates.push_back(std::move(CT));
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return;
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}
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case ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR: {
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// Select back-to-back non-memory instruction.
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for (const auto OtherInstr :
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computeAliasingInstructions(State, Instr, kMaxAliasingInstructions)) {
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const AliasingConfigurations Forward(Instr, OtherInstr);
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const AliasingConfigurations Back(OtherInstr, Instr);
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InstructionTemplate ThisIT(Instr);
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InstructionTemplate OtherIT(OtherInstr);
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if (!Forward.hasImplicitAliasing())
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setRandomAliasing(Forward, ThisIT, OtherIT);
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if (!Back.hasImplicitAliasing())
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setRandomAliasing(Back, OtherIT, ThisIT);
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CodeTemplate CT;
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CT.Execution = ExecutionModeBit;
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CT.Info = ExecutionClassDescription;
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CT.Instructions.push_back(std::move(ThisIT));
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CT.Instructions.push_back(std::move(OtherIT));
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CodeTemplates.push_back(std::move(CT));
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}
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return;
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}
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default:
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llvm_unreachable("Unhandled enum value");
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}
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}
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LatencySnippetGenerator::~LatencySnippetGenerator() = default;
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llvm::Expected<std::vector<CodeTemplate>>
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LatencySnippetGenerator::generateCodeTemplates(const Instruction &Instr) const {
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if (Instr.hasMemoryOperands())
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std::vector<CodeTemplate> Results;
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const ExecutionMode EM = getExecutionModes(Instr);
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for (const auto EC : kExecutionClasses) {
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for (const auto ExecutionModeBit : getExecutionModeBits(EM & EC.Mask))
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appendCodeTemplates(State, Instr, ExecutionModeBit, EC.Description,
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Results);
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if (!Results.empty())
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break;
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}
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if (Results.empty())
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return llvm::make_error<BenchmarkFailure>(
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"Infeasible : has memory operands");
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return llvm::handleExpected( //
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generateSelfAliasingCodeTemplates(Instr),
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[this, &Instr]() {
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return generateTwoInstructionPrototypes(State, Instr);
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},
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[](const BenchmarkFailure &) { /*Consume Error*/ });
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"No strategy found to make the execution serial");
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return std::move(Results);
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}
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const char *LatencyBenchmarkRunner::getCounterName() const {
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@ -27,7 +27,14 @@ unsigned Variable::getPrimaryOperandIndex() const {
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return TiedOperands[0];
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}
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bool Variable::hasTiedOperands() const { return TiedOperands.size() > 1; }
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bool Variable::hasTiedOperands() const {
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assert(TiedOperands.size() <= 2 &&
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"No more than two operands can be tied together");
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// By definition only Use and Def operands can be tied together.
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// TiedOperands[0] is the Def operand (LLVM stores defs first).
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// TiedOperands[1] is the Use operand.
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return TiedOperands.size() > 1;
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}
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unsigned Operand::getIndex() const {
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assert(Index >= 0 && "Index must be set");
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@ -197,6 +204,10 @@ bool Instruction::hasAliasingRegisters() const {
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return AllDefRegs.anyCommon(AllUseRegs);
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}
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bool Instruction::hasOneUseOrOneDef() const {
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return AllDefRegs.count() || AllUseRegs.count();
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}
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void Instruction::dump(const llvm::MCRegisterInfo &RegInfo,
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llvm::raw_ostream &Stream) const {
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Stream << "- " << Name << "\n";
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@ -288,8 +299,7 @@ bool AliasingConfigurations::hasImplicitAliasing() const {
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}
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AliasingConfigurations::AliasingConfigurations(
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const Instruction &DefInstruction, const Instruction &UseInstruction)
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: DefInstruction(DefInstruction), UseInstruction(UseInstruction) {
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const Instruction &DefInstruction, const Instruction &UseInstruction) {
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if (UseInstruction.AllUseRegs.anyCommon(DefInstruction.AllDefRegs)) {
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auto CommonRegisters = UseInstruction.AllUseRegs;
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CommonRegisters &= DefInstruction.AllDefRegs;
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@ -125,6 +125,11 @@ struct Instruction {
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// reads or write the same memory region.
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bool hasMemoryOperands() const;
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// Returns whether this instruction as at least one use or one def.
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// Repeating this instruction may execute sequentially by adding an
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// instruction that aliases one of these.
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bool hasOneUseOrOneDef() const;
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// Convenient function to help with debugging.
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void dump(const llvm::MCRegisterInfo &RegInfo,
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llvm::raw_ostream &Stream) const;
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@ -174,10 +179,7 @@ struct AliasingConfigurations {
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bool empty() const; // True if no aliasing configuration is found.
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bool hasImplicitAliasing() const;
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void setExplicitAliasing() const;
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const Instruction &DefInstruction;
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const Instruction &UseInstruction;
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llvm::SmallVector<AliasingRegisterOperands, 32> Configurations;
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};
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@ -22,7 +22,7 @@
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namespace exegesis {
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std::vector<CodeTemplate> getSingleton(CodeTemplate &CT) {
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std::vector<CodeTemplate> getSingleton(CodeTemplate &&CT) {
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std::vector<CodeTemplate> Result;
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Result.push_back(std::move(CT));
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return Result;
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@ -30,7 +30,7 @@
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namespace exegesis {
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std::vector<CodeTemplate> getSingleton(CodeTemplate &CT);
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std::vector<CodeTemplate> getSingleton(CodeTemplate &&CT);
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// Generates code templates that has a self-dependency.
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llvm::Expected<std::vector<CodeTemplate>>
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@ -153,13 +153,13 @@ UopsSnippetGenerator::generateCodeTemplates(const Instruction &Instr) const {
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CT.Info = "instruction is parallel, repeating a random one.";
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CT.Instructions.push_back(std::move(IT));
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instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
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return getSingleton(CT);
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return getSingleton(std::move(CT));
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}
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if (SelfAliasing.hasImplicitAliasing()) {
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CT.Info = "instruction is serial, repeating a random one.";
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CT.Instructions.push_back(std::move(IT));
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instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
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return getSingleton(CT);
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return getSingleton(std::move(CT));
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}
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const auto TiedVariables = getVariablesWithTiedOperands(Instr);
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if (!TiedVariables.empty()) {
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@ -181,7 +181,7 @@ UopsSnippetGenerator::generateCodeTemplates(const Instruction &Instr) const {
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CT.Instructions.push_back(std::move(TmpIT));
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}
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instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
|
||||
return getSingleton(CT);
|
||||
return getSingleton(std::move(CT));
|
||||
}
|
||||
const auto &ReservedRegisters = State.getRATC().reservedRegisters();
|
||||
// No tied variables, we pick random values for defs.
|
||||
@ -218,7 +218,7 @@ UopsSnippetGenerator::generateCodeTemplates(const Instruction &Instr) const {
|
||||
"instruction has no tied variables picking Uses different from defs";
|
||||
CT.Instructions.push_back(std::move(IT));
|
||||
instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
|
||||
return getSingleton(CT);
|
||||
return getSingleton(std::move(CT));
|
||||
}
|
||||
|
||||
std::vector<BenchmarkMeasure>
|
||||
|
||||
@ -25,6 +25,7 @@ namespace {
|
||||
|
||||
using testing::AnyOf;
|
||||
using testing::ElementsAre;
|
||||
using testing::Gt;
|
||||
using testing::HasSubstr;
|
||||
using testing::Not;
|
||||
using testing::SizeIs;
|
||||
@ -57,14 +58,12 @@ class SnippetGeneratorTest : public X86SnippetGeneratorTest {
|
||||
protected:
|
||||
SnippetGeneratorTest() : Generator(State) {}
|
||||
|
||||
CodeTemplate checkAndGetCodeTemplate(unsigned Opcode) {
|
||||
std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
|
||||
randomGenerator().seed(0); // Initialize seed.
|
||||
const Instruction Instr(State, Opcode);
|
||||
auto CodeTemplateOrError = Generator.generateCodeTemplates(Instr);
|
||||
EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
|
||||
auto &CodeTemplate = CodeTemplateOrError.get();
|
||||
EXPECT_EQ(CodeTemplate.size(), 1U);
|
||||
return std::move(CodeTemplate.front());
|
||||
return std::move(CodeTemplateOrError.get());
|
||||
}
|
||||
|
||||
SnippetGeneratorT Generator;
|
||||
@ -75,21 +74,25 @@ using LatencySnippetGeneratorTest =
|
||||
|
||||
using UopsSnippetGeneratorTest = SnippetGeneratorTest<UopsSnippetGenerator>;
|
||||
|
||||
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependency) {
|
||||
// ADC16i16 self alias because of implicit use and def.
|
||||
|
||||
// explicit use 0 : imm
|
||||
// implicit def : AX
|
||||
// implicit def : EFLAGS
|
||||
// implicit use : AX
|
||||
// implicit use : EFLAGS
|
||||
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
|
||||
// - ADC16i16
|
||||
// - Op0 Explicit Use Immediate
|
||||
// - Op1 Implicit Def Reg(AX)
|
||||
// - Op2 Implicit Def Reg(EFLAGS)
|
||||
// - Op3 Implicit Use Reg(AX)
|
||||
// - Op4 Implicit Use Reg(EFLAGS)
|
||||
// - Var0 [Op0]
|
||||
// - hasAliasingImplicitRegisters (execution is always serial)
|
||||
// - hasAliasingRegisters
|
||||
const unsigned Opcode = llvm::X86::ADC16i16;
|
||||
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::AX);
|
||||
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[1], llvm::X86::EFLAGS);
|
||||
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[0], llvm::X86::AX);
|
||||
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitUses()[1], llvm::X86::EFLAGS);
|
||||
const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
|
||||
EXPECT_THAT(CT.Info, HasSubstr("implicit"));
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(1));
|
||||
const auto &CT = CodeTemplates[0];
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS);
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
@ -97,63 +100,105 @@ TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependency) {
|
||||
EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Immediate is not set";
|
||||
}
|
||||
|
||||
TEST_F(LatencySnippetGeneratorTest, ExplicitSelfDependency) {
|
||||
// ADD16ri self alias because Op0 and Op1 are tied together.
|
||||
|
||||
// explicit def 0 : reg RegClass=GR16
|
||||
// explicit use 1 : reg RegClass=GR16 | TIED_TO:0
|
||||
// explicit use 2 : imm
|
||||
// implicit def : EFLAGS
|
||||
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
|
||||
// - ADD16ri
|
||||
// - Op0 Explicit Def RegClass(GR16)
|
||||
// - Op1 Explicit Use RegClass(GR16) TiedToOp0
|
||||
// - Op2 Explicit Use Immediate
|
||||
// - Op3 Implicit Def Reg(EFLAGS)
|
||||
// - Var0 [Op0,Op1]
|
||||
// - Var1 [Op2]
|
||||
// - hasTiedRegisters (execution is always serial)
|
||||
// - hasAliasingRegisters
|
||||
const unsigned Opcode = llvm::X86::ADD16ri;
|
||||
EXPECT_THAT(MCInstrInfo.get(Opcode).getImplicitDefs()[0], llvm::X86::EFLAGS);
|
||||
const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
|
||||
EXPECT_THAT(CT.Info, HasSubstr("explicit"));
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(1));
|
||||
const auto &CT = CodeTemplates[0];
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(2));
|
||||
EXPECT_THAT(IT.VariableValues[0], IsReg()) << "Operand 0 and 1";
|
||||
EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Operand 1 is not set";
|
||||
EXPECT_THAT(IT.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
|
||||
}
|
||||
|
||||
TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) {
|
||||
// CMP64rr
|
||||
// explicit use 0 : reg RegClass=GR64
|
||||
// explicit use 1 : reg RegClass=GR64
|
||||
// implicit def : EFLAGS
|
||||
|
||||
const unsigned Opcode = llvm::X86::CMP64rr;
|
||||
const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
|
||||
EXPECT_THAT(CT.Info, HasSubstr("cycle through"));
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(2));
|
||||
TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
|
||||
// - VXORPSrr
|
||||
// - Op0 Explicit Def RegClass(VR128)
|
||||
// - Op1 Explicit Use RegClass(VR128)
|
||||
// - Op2 Explicit Use RegClass(VR128)
|
||||
// - Var0 [Op0]
|
||||
// - Var1 [Op1]
|
||||
// - Var2 [Op2]
|
||||
// - hasAliasingRegisters
|
||||
const unsigned Opcode = llvm::X86::VXORPSrr;
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(1));
|
||||
const auto &CT = CodeTemplates[0];
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(2));
|
||||
EXPECT_THAT(IT.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
|
||||
ElementsAre(IsInvalid(), IsReg())));
|
||||
EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
|
||||
// TODO: check that the two instructions alias each other.
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(3));
|
||||
EXPECT_THAT(IT.VariableValues,
|
||||
AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
|
||||
ElementsAre(IsReg(), IsReg(), IsInvalid())))
|
||||
<< "Op0 is either set to Op1 or to Op2";
|
||||
}
|
||||
|
||||
TEST_F(LatencySnippetGeneratorTest, DependencyThroughOtherOpcode) {
|
||||
// - CMP64rr
|
||||
// - Op0 Explicit Use RegClass(GR64)
|
||||
// - Op1 Explicit Use RegClass(GR64)
|
||||
// - Op2 Implicit Def Reg(EFLAGS)
|
||||
// - Var0 [Op0]
|
||||
// - Var1 [Op1]
|
||||
const unsigned Opcode = llvm::X86::CMP64rr;
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
|
||||
for (const auto &CT : CodeTemplates) {
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(2));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(2));
|
||||
EXPECT_THAT(IT.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
|
||||
ElementsAre(IsInvalid(), IsReg())));
|
||||
EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
|
||||
// TODO: check that the two instructions alias each other.
|
||||
}
|
||||
}
|
||||
|
||||
TEST_F(LatencySnippetGeneratorTest, LAHF) {
|
||||
// - LAHF
|
||||
// - Op0 Implicit Def Reg(AH)
|
||||
// - Op1 Implicit Use Reg(EFLAGS)
|
||||
const unsigned Opcode = llvm::X86::LAHF;
|
||||
const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
|
||||
EXPECT_THAT(CT.Info, HasSubstr("cycle through"));
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(2));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(0));
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
|
||||
for (const auto &CT : CodeTemplates) {
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(2));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
ASSERT_THAT(IT.VariableValues, SizeIs(0));
|
||||
}
|
||||
}
|
||||
|
||||
TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) {
|
||||
// BNDCL32rr is parallel no matter what.
|
||||
|
||||
// explicit use 0 : reg RegClass=BNDR
|
||||
// explicit use 1 : reg RegClass=GR32
|
||||
|
||||
// - BNDCL32rr
|
||||
// - Op0 Explicit Use RegClass(BNDR)
|
||||
// - Op1 Explicit Use RegClass(GR32)
|
||||
// - Var0 [Op0]
|
||||
// - Var1 [Op1]
|
||||
const unsigned Opcode = llvm::X86::BNDCL32rr;
|
||||
const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(1));
|
||||
const auto &CT = CodeTemplates[0];
|
||||
EXPECT_THAT(CT.Info, HasSubstr("parallel"));
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
@ -163,14 +208,18 @@ TEST_F(UopsSnippetGeneratorTest, ParallelInstruction) {
|
||||
}
|
||||
|
||||
TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
|
||||
// CDQ is serial no matter what.
|
||||
|
||||
// implicit def : EAX
|
||||
// implicit def : EDX
|
||||
// implicit use : EAX
|
||||
// - CDQ
|
||||
// - Op0 Implicit Def Reg(EAX)
|
||||
// - Op1 Implicit Def Reg(EDX)
|
||||
// - Op2 Implicit Use Reg(EAX)
|
||||
// - hasAliasingImplicitRegisters (execution is always serial)
|
||||
// - hasAliasingRegisters
|
||||
const unsigned Opcode = llvm::X86::CDQ;
|
||||
const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(1));
|
||||
const auto &CT = CodeTemplates[0];
|
||||
EXPECT_THAT(CT.Info, HasSubstr("serial"));
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
@ -181,13 +230,21 @@ TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
|
||||
// CMOVA32rr has tied variables, we enumerate the possible values to execute
|
||||
// as many in parallel as possible.
|
||||
|
||||
// explicit def 0 : reg RegClass=GR32
|
||||
// explicit use 1 : reg RegClass=GR32 | TIED_TO:0
|
||||
// explicit use 2 : reg RegClass=GR32
|
||||
// implicit use : EFLAGS
|
||||
// - CMOVA32rr
|
||||
// - Op0 Explicit Def RegClass(GR32)
|
||||
// - Op1 Explicit Use RegClass(GR32) TiedToOp0
|
||||
// - Op2 Explicit Use RegClass(GR32)
|
||||
// - Op3 Implicit Use Reg(EFLAGS)
|
||||
// - Var0 [Op0,Op1]
|
||||
// - Var1 [Op2]
|
||||
// - hasTiedRegisters (execution is always serial)
|
||||
// - hasAliasingRegisters
|
||||
const unsigned Opcode = llvm::X86::CMOVA32rr;
|
||||
const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(1));
|
||||
const auto &CT = CodeTemplates[0];
|
||||
EXPECT_THAT(CT.Info, HasSubstr("static renaming"));
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
|
||||
constexpr const unsigned kInstructionCount = 15;
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
|
||||
std::unordered_set<unsigned> AllDefRegisters;
|
||||
@ -203,14 +260,23 @@ TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
|
||||
// CMOV_GR32 has no tied variables, we make sure def and use are different
|
||||
// from each other.
|
||||
|
||||
// explicit def 0 : reg RegClass=GR32
|
||||
// explicit use 1 : reg RegClass=GR32
|
||||
// explicit use 2 : reg RegClass=GR32
|
||||
// explicit use 3 : imm
|
||||
// implicit use : EFLAGS
|
||||
// - CMOV_GR32
|
||||
// - Op0 Explicit Def RegClass(GR32)
|
||||
// - Op1 Explicit Use RegClass(GR32)
|
||||
// - Op2 Explicit Use RegClass(GR32)
|
||||
// - Op3 Explicit Use Immediate
|
||||
// - Op4 Implicit Use Reg(EFLAGS)
|
||||
// - Var0 [Op0]
|
||||
// - Var1 [Op1]
|
||||
// - Var2 [Op2]
|
||||
// - Var3 [Op3]
|
||||
// - hasAliasingRegisters
|
||||
const unsigned Opcode = llvm::X86::CMOV_GR32;
|
||||
const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(1));
|
||||
const auto &CT = CodeTemplates[0];
|
||||
EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
|
||||
ASSERT_THAT(CT.Instructions, SizeIs(1));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
EXPECT_THAT(IT.getOpcode(), Opcode);
|
||||
@ -224,9 +290,27 @@ TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
|
||||
|
||||
TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
|
||||
// Mov32rm reads from memory.
|
||||
// - MOV32rm
|
||||
// - Op0 Explicit Def RegClass(GR32)
|
||||
// - Op1 Explicit Use Memory RegClass(GR8)
|
||||
// - Op2 Explicit Use Memory
|
||||
// - Op3 Explicit Use Memory RegClass(GRH8)
|
||||
// - Op4 Explicit Use Memory
|
||||
// - Op5 Explicit Use Memory RegClass(SEGMENT_REG)
|
||||
// - Var0 [Op0]
|
||||
// - Var1 [Op1]
|
||||
// - Var2 [Op2]
|
||||
// - Var3 [Op3]
|
||||
// - Var4 [Op4]
|
||||
// - Var5 [Op5]
|
||||
// - hasMemoryOperands
|
||||
// - hasAliasingRegisters
|
||||
const unsigned Opcode = llvm::X86::MOV32rm;
|
||||
const CodeTemplate CT = checkAndGetCodeTemplate(Opcode);
|
||||
const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
|
||||
ASSERT_THAT(CodeTemplates, SizeIs(1));
|
||||
const auto &CT = CodeTemplates[0];
|
||||
EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
|
||||
EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
|
||||
ASSERT_THAT(CT.Instructions,
|
||||
SizeIs(UopsSnippetGenerator::kMinNumDifferentAddresses));
|
||||
const InstructionTemplate &IT = CT.Instructions[0];
|
||||
@ -240,6 +324,21 @@ TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
|
||||
|
||||
TEST_F(UopsSnippetGeneratorTest, MemoryUse_Movsb) {
|
||||
// MOVSB writes to scratch memory register.
|
||||
// - MOVSB
|
||||
// - Op0 Explicit Use Memory RegClass(GR8)
|
||||
// - Op1 Explicit Use Memory RegClass(GR8)
|
||||
// - Op2 Explicit Use Memory RegClass(SEGMENT_REG)
|
||||
// - Op3 Implicit Def Reg(EDI)
|
||||
// - Op4 Implicit Def Reg(ESI)
|
||||
// - Op5 Implicit Use Reg(EDI)
|
||||
// - Op6 Implicit Use Reg(ESI)
|
||||
// - Op7 Implicit Use Reg(DF)
|
||||
// - Var0 [Op0]
|
||||
// - Var1 [Op1]
|
||||
// - Var2 [Op2]
|
||||
// - hasMemoryOperands
|
||||
// - hasAliasingImplicitRegisters (execution is always serial)
|
||||
// - hasAliasingRegisters
|
||||
const unsigned Opcode = llvm::X86::MOVSB;
|
||||
const Instruction Instr(State, Opcode);
|
||||
auto Error = Generator.generateCodeTemplates(Instr).takeError();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user