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Rename the opCode instance variable to Opcode
llvm-svn: 11348
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04c37927bd
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@ -332,7 +332,7 @@ private:
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//===----------------------------------------------------------------------===//
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class MachineInstr {
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int opCode; // the opcode
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int Opcode; // the opcode
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std::vector<MachineOperand> operands; // the operands
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unsigned numImplicitRefs; // number of implicit operands
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MachineInstr* prev, *next; // links for our intrusive list
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@ -371,7 +371,7 @@ public:
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/// Accessors for opcode.
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///
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const int getOpcode() const { return opCode; }
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const int getOpcode() const { return Opcode; }
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/// Access to explicit operands of the instruction.
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///
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@ -591,7 +591,7 @@ public:
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/// setOpcode - Replace the opcode of the current instruction with a new one.
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///
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void setOpcode(unsigned Op) { opCode = Op; }
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void setOpcode(unsigned Op) { Opcode = Op; }
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/// RemoveOperand - Erase an operand from an instruction, leaving it with one
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/// fewer operand than it started with.
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@ -28,11 +28,8 @@ namespace llvm {
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extern const TargetInstrDescriptor *TargetInstrDescriptors;
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// Constructor for instructions with variable #operands
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MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
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: opCode(OpCode),
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operands(numOperands, MachineOperand()),
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numImplicitRefs(0)
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{
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MachineInstr::MachineInstr(MachineOpCode opcode, unsigned numOperands)
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: Opcode(opcode), operands(numOperands, MachineOperand()), numImplicitRefs(0){
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}
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/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
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@ -40,22 +37,18 @@ MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
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/// add* methods below to fill up the operands, instead of the Set methods.
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/// Eventually, the "resizing" ctors will be phased out.
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///
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MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
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MachineInstr::MachineInstr(MachineOpCode opcode, unsigned numOperands,
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bool XX, bool YY)
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: opCode(Opcode),
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numImplicitRefs(0)
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{
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: Opcode(opcode), numImplicitRefs(0) {
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operands.reserve(numOperands);
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}
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
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/// MachineInstr is created and added to the end of the specified basic block.
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///
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode opcode,
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unsigned numOperands)
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: opCode(Opcode),
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numImplicitRefs(0)
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{
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: Opcode(opcode), numImplicitRefs(0) {
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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operands.reserve(numOperands);
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MBB->push_back(this); // Add instruction to end of basic block!
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@ -63,9 +56,8 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
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// OperandComplete - Return true if it's illegal to add a new operand
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bool MachineInstr::OperandsComplete() const
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{
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int NumOperands = TargetInstrDescriptors[opCode].numOperands;
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bool MachineInstr::OperandsComplete() const {
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int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
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if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
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return true; // Broken: we have all the operands of this instruction!
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return false;
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@ -77,11 +69,10 @@ bool MachineInstr::OperandsComplete() const
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// This only resets the size of the operand vector and initializes it.
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// The new operands must be set explicitly later.
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//
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void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
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{
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void MachineInstr::replace(MachineOpCode opcode, unsigned numOperands) {
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assert(getNumImplicitRefs() == 0 &&
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"This is probably broken because implicit refs are going to be lost.");
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opCode = Opcode;
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Opcode = opcode;
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operands.clear();
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operands.resize(numOperands, MachineOperand());
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}
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@ -98,10 +89,9 @@ void MachineInstr::SetMachineOperandVal(unsigned i,
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void
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MachineInstr::SetMachineOperandConst(unsigned i,
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MachineOperand::MachineOperandType operandType,
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int64_t intValue)
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{
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int64_t intValue) {
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assert(i < getNumOperands()); // must be explicit op
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assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
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assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
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"immed. constant cannot be defined");
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operands[i].opType = operandType;
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@ -119,16 +109,12 @@ void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
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operands[i].regNum = regNum;
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}
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void
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MachineInstr::SetRegForOperand(unsigned i, int regNum)
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{
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void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
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assert(i < getNumOperands()); // must be explicit op
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operands[i].setRegForValue(regNum);
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}
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void
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MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
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{
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void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
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getImplicitOp(i).setRegForValue(regNum);
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}
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@ -327,7 +313,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
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std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
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{
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os << TargetInstrDescriptors[MI.opCode].Name;
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os << TargetInstrDescriptors[MI.getOpcode()].Name;
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for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
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os << "\t" << MI.getOperand(i);
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