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[x86] add more tests for horizontal ops; NFC
llvm-svn: 312279
This commit is contained in:
Sanjay Patel
parent
0e2bd8153d
commit
ef5b613038
159
test/CodeGen/X86/haddsub-shuf.ll
Normal file
159
test/CodeGen/X86/haddsub-shuf.ll
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@ -0,0 +1,159 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; The next 8 tests check for matching the horizontal op and eliminating the shuffle.
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; PR34111 - https://bugs.llvm.org/show_bug.cgi?id=34111
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define <4 x float> @hadd_v4f32(<4 x float> %a) {
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; SSSE3-LABEL: hadd_v4f32:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: haddps %xmm0, %xmm0
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; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hadd_v4f32:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX-NEXT: retq
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%a02 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 2>
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%a13 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 1, i32 3>
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%hop = fadd <2 x float> %a02, %a13
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%shuf = shufflevector <2 x float> %hop, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
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ret <4 x float> %shuf
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}
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define <4 x float> @hsub_v4f32(<4 x float> %a) {
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; SSSE3-LABEL: hsub_v4f32:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: hsubps %xmm0, %xmm0
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; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hsub_v4f32:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX-NEXT: retq
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%a02 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 2>
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%a13 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 1, i32 3>
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%hop = fsub <2 x float> %a02, %a13
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%shuf = shufflevector <2 x float> %hop, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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ret <4 x float> %shuf
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}
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define <2 x double> @hadd_v2f64(<2 x double> %a) {
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; SSSE3-LABEL: hadd_v2f64:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: haddpd %xmm0, %xmm0
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; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hadd_v2f64:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX-NEXT: retq
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%a0 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
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%a1 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
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%hop = fadd <2 x double> %a0, %a1
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%shuf = shufflevector <2 x double> %hop, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x double> %shuf
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}
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define <2 x double> @hsub_v2f64(<2 x double> %a) {
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; SSSE3-LABEL: hsub_v2f64:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: hsubpd %xmm0, %xmm0
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; SSSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hsub_v2f64:
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; AVX: # BB#0:
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; AVX-NEXT: vhsubpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX-NEXT: retq
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%a0 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
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%a1 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
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%hop = fsub <2 x double> %a0, %a1
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%shuf = shufflevector <2 x double> %hop, <2 x double> undef, <2 x i32> <i32 undef, i32 0>
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ret <2 x double> %shuf
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}
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define <4 x i32> @hadd_v4i32(<4 x i32> %a) {
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; SSSE3-LABEL: hadd_v4i32:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: phaddd %xmm0, %xmm0
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hadd_v4i32:
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; AVX: # BB#0:
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; AVX-NEXT: vphaddd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; AVX-NEXT: retq
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%a02 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%a13 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%hop = add <4 x i32> %a02, %a13
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%shuf = shufflevector <4 x i32> %hop, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 1>
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ret <4 x i32> %shuf
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}
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define <4 x i32> @hsub_v4i32(<4 x i32> %a) {
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; SSSE3-LABEL: hsub_v4i32:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: phsubd %xmm0, %xmm0
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hsub_v4i32:
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; AVX: # BB#0:
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; AVX-NEXT: vphsubd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; AVX-NEXT: retq
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%a02 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%a13 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%hop = sub <4 x i32> %a02, %a13
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%shuf = shufflevector <4 x i32> %hop, <4 x i32> undef, <4 x i32> <i32 undef, i32 1, i32 0, i32 undef>
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ret <4 x i32> %shuf
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}
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define <8 x i16> @hadd_v8i16(<8 x i16> %a) {
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; SSSE3-LABEL: hadd_v8i16:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: phaddw %xmm0, %xmm0
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hadd_v8i16:
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; AVX: # BB#0:
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; AVX-NEXT: vphaddw %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; AVX-NEXT: retq
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%a0246 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
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%a1357 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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%hop = add <8 x i16> %a0246, %a1357
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%shuf = shufflevector <8 x i16> %hop, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3>
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ret <8 x i16> %shuf
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}
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define <8 x i16> @hsub_v8i16(<8 x i16> %a) {
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; SSSE3-LABEL: hsub_v8i16:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: phsubw %xmm0, %xmm0
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: hsub_v8i16:
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; AVX: # BB#0:
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; AVX-NEXT: vphsubw %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
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; AVX-NEXT: retq
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%a0246 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>
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%a1357 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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%hop = sub <8 x i16> %a0246, %a1357
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%shuf = shufflevector <8 x i16> %hop, <8 x i16> undef, <8 x i32> <i32 0, i32 undef, i32 2, i32 undef, i32 undef, i32 1, i32 undef, i32 3>
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ret <8 x i16> %shuf
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}
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@ -398,22 +398,3 @@ define <2 x float> @haddps_v2f32(<4 x float> %v0) {
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ret <2 x float> %res1
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}
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define <4 x float> @PR34111(<4 x float> %a) {
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; SSE3-LABEL: PR34111:
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; SSE3: # BB#0:
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; SSE3-NEXT: haddps %xmm0, %xmm0
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; SSE3-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
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; SSE3-NEXT: retq
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;
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; AVX-LABEL: PR34111:
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; AVX: # BB#0:
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; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX-NEXT: retq
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%a02 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 2>
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%a13 = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 1, i32 3>
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%add = fadd <2 x float> %a02, %a13
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%hadd = shufflevector <2 x float> %add, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
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ret <4 x float> %hadd
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}
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