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ARM: Add ImmArg to intrinsics
I found these by asserting in clang for any GCCBuiltin that doesn't require mangling and requires a constant for the builtin. This means that intrinsics are missing which don't use GCCBuiltin, don't have builtins defined in clang, or were missing the constant annotation in the builtin definition. llvm-svn: 356144
This commit is contained in:
Matt Arsenault
parent
fd11c30e7f
commit
ef9e376272
@ -262,59 +262,59 @@ def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
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// Coprocessor
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def int_arm_ldc : GCCBuiltin<"__builtin_arm_ldc">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>;
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def int_arm_ldcl : GCCBuiltin<"__builtin_arm_ldcl">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>;
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def int_arm_ldc2 : GCCBuiltin<"__builtin_arm_ldc2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>;
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def int_arm_ldc2l : GCCBuiltin<"__builtin_arm_ldc2l">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>;
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def int_arm_stc : GCCBuiltin<"__builtin_arm_stc">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>;
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def int_arm_stcl : GCCBuiltin<"__builtin_arm_stcl">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>;
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def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>;
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def int_arm_stc2l : GCCBuiltin<"__builtin_arm_stc2l">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], []>;
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<0>, ImmArg<1>]>;
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// Move to coprocessor
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def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
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def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
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// Move from coprocessor
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def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
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MSBuiltin<"_MoveFromCoprocessor">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>, ImmArg<3>, ImmArg<4>]>;
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def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
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MSBuiltin<"_MoveFromCoprocessor2">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>, ImmArg<3>, ImmArg<4>]>;
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// Coprocessor data processing
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def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
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def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
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// Move from two registers to coprocessor
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def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<4>]>;
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def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<4>]>;
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def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>]>;
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def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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llvm_i32_ty, llvm_i32_ty], [ImmArg<0>, ImmArg<1>, ImmArg<2>]>;
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//===----------------------------------------------------------------------===//
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// CRC32
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@ -1,13 +0,0 @@
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; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
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; RUN: not llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
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; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp
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define void @cdp(i32 %a) #0 {
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%1 = load i32, i32* %a.addr, align 4
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call void @llvm.arm.cdp(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
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ret void
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}
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declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
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@ -1,13 +0,0 @@
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; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
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; RUN: not llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
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; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp2
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define void @cdp2(i32 %a) #0 {
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%1 = load i32, i32* %a.addr, align 4
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call void @llvm.arm.cdp2(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
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ret void
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}
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declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
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102
test/Verifier/ARM/intrinsic-immarg.ll
Normal file
102
test/Verifier/ARM/intrinsic-immarg.ll
Normal file
@ -0,0 +1,102 @@
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; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s
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declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
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define void @cdp(i32 %a) #0 {
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: %load = load i32, i32* %a.addr, align 4
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; CHECK-NEXT: call void @llvm.arm.cdp(i32 %load, i32 2, i32 3, i32 4, i32 5, i32 6)
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%load = load i32, i32* %a.addr, align 4
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call void @llvm.arm.cdp(i32 %load, i32 2, i32 3, i32 4, i32 5, i32 6)
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ret void
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}
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declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
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define void @cdp2(i32 %a) #0 {
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: %load = load i32, i32* %a.addr, align 4
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; CHECK-NEXT: call void @llvm.arm.cdp2(i32 %load, i32 2, i32 3, i32 4, i32 5, i32 6)
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%load = load i32, i32* %a.addr, align 4
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call void @llvm.arm.cdp2(i32 %load, i32 2, i32 3, i32 4, i32 5, i32 6)
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ret void
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}
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declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind
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define void @mrrc(i32 %arg0, i32 %arg1, i32 %arg2) #0 {
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg0
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; CHECK-NEXT: %ret0 = call { i32, i32 } @llvm.arm.mrrc(i32 %arg0, i32 0, i32 0)
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%ret0 = call { i32, i32 } @llvm.arm.mrrc(i32 %arg0, i32 0, i32 0)
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg1
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; CHECK-NEXT: %ret1 = call { i32, i32 } @llvm.arm.mrrc(i32 0, i32 %arg1, i32 0)
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%ret1 = call { i32, i32 } @llvm.arm.mrrc(i32 0, i32 %arg1, i32 0)
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg2
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; CHECK-NEXT: %ret2 = call { i32, i32 } @llvm.arm.mrrc(i32 0, i32 0, i32 %arg2)
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%ret2 = call { i32, i32 } @llvm.arm.mrrc(i32 0, i32 0, i32 %arg2)
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ret void
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}
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declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind
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define void @mrrc2(i32 %arg0, i32 %arg1, i32 %arg2) #0 {
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg0
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; CHECK-NEXT: %ret0 = call { i32, i32 } @llvm.arm.mrrc2(i32 %arg0, i32 0, i32 0)
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%ret0 = call { i32, i32 } @llvm.arm.mrrc2(i32 %arg0, i32 0, i32 0)
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg1
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; CHECK-NEXT: %ret1 = call { i32, i32 } @llvm.arm.mrrc2(i32 0, i32 %arg1, i32 0)
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%ret1 = call { i32, i32 } @llvm.arm.mrrc2(i32 0, i32 %arg1, i32 0)
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg2
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; CHECK-NEXT: %ret2 = call { i32, i32 } @llvm.arm.mrrc2(i32 0, i32 0, i32 %arg2)
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%ret2 = call { i32, i32 } @llvm.arm.mrrc2(i32 0, i32 0, i32 %arg2)
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ret void
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}
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declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
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define void @mcrr(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg0
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; CHECK-NEXT: call void @llvm.arm.mcrr(i32 %arg0, i32 1, i32 2, i32 3, i32 4)
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call void @llvm.arm.mcrr(i32 %arg0, i32 1, i32 2, i32 3, i32 4)
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg1
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; CHECK-NEXT: call void @llvm.arm.mcrr(i32 0, i32 %arg1, i32 2, i32 3, i32 4)
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call void @llvm.arm.mcrr(i32 0, i32 %arg1, i32 2, i32 3, i32 4)
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg4
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; CHECK-NEXT: call void @llvm.arm.mcrr(i32 0, i32 1, i32 2, i32 3, i32 %arg4)
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call void @llvm.arm.mcrr(i32 0, i32 1, i32 2, i32 3, i32 %arg4)
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ret void
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}
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declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
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define void @mcrr2(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg0
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; CHECK-NEXT: call void @llvm.arm.mcrr2(i32 %arg0, i32 1, i32 2, i32 3, i32 4)
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call void @llvm.arm.mcrr2(i32 %arg0, i32 1, i32 2, i32 3, i32 4)
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg1
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; CHECK-NEXT: call void @llvm.arm.mcrr2(i32 0, i32 %arg1, i32 2, i32 3, i32 4)
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call void @llvm.arm.mcrr2(i32 0, i32 %arg1, i32 2, i32 3, i32 4)
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; CHECK: immarg operand has non-immediate parameter
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; CHECK-NEXT: i32 %arg4
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; CHECK-NEXT: call void @llvm.arm.mcrr2(i32 0, i32 1, i32 2, i32 3, i32 %arg4)
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call void @llvm.arm.mcrr2(i32 0, i32 1, i32 2, i32 3, i32 %arg4)
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ret void
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}
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2
test/Verifier/ARM/lit.local.cfg
Normal file
2
test/Verifier/ARM/lit.local.cfg
Normal file
@ -0,0 +1,2 @@
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if not 'ARM' in config.root.targets:
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config.unsupported = True
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