RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-27 05:55:40 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Remove some dead code from SPU BE that remained

Browse Source 
from 64bit vector support.

llvm-svn: 111910
This commit is contained in:
Kalle Raiskila 2010-08-24 11:05:51 +00:00
parent 4e49cb4a11
commit ef9e592448
3 changed files with 6 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -514,8 +514,6 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
node_names[(unsigned) SPUISD::ADD64_MARKER] = "SPUISD::ADD64_MARKER";
node_names[(unsigned) SPUISD::SUB64_MARKER] = "SPUISD::SUB64_MARKER";
node_names[(unsigned) SPUISD::MUL64_MARKER] = "SPUISD::MUL64_MARKER";
node_names[(unsigned) SPUISD::HALF2VEC] = "SPUISD::HALF2VEC";
node_names[(unsigned) SPUISD::VEC2HALF] = "SPUISD::VEC2HALF";
}
std::map<unsigned, const char *>::iterator i = node_names.find(Opcode);
@ -736,14 +734,12 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
DebugLoc dl = Op.getDebugLoc();
unsigned alignment = SN->getAlignment();
const bool isVec = VT.isVector();
EVT eltTy = isVec ? VT.getVectorElementType(): VT;
switch (SN->getAddressingMode()) {
case ISD::UNINDEXED: {
// The vector type we really want to load from the 16-byte chunk.
EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
eltTy, (128 / eltTy.getSizeInBits()));
VT, (128 / VT.getSizeInBits()));
SDValue alignLoadVec;
SDValue basePtr = SN->getBasePtr();
@ -846,19 +842,11 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
}
#endif
SDValue insertEltOp;
SDValue vectorizeOp;
if (isVec)
{
// FIXME: this works only if the vector is 64bit!
insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v2i64, insertEltOffs);
vectorizeOp = DAG.getNode(SPUISD::HALF2VEC, dl, vecVT, theValue);
}
else
{
insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs);
vectorizeOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue);
}
SDValue insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT,
insertEltOffs);
SDValue vectorizeOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT,
theValue);
result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
vectorizeOp, alignLoadVec,
DAG.getNode(ISD::BIT_CONVERT, dl,

2
lib/Target/CellSPU/SPUISelLowering.h
View File

@ -54,8 +54,6 @@ namespace llvm {
ADD64_MARKER, ///< i64 addition marker
SUB64_MARKER, ///< i64 subtraction marker
MUL64_MARKER, ///< i64 multiply marker
HALF2VEC, ///< Promote 64 bit vector to 128 bits
VEC2HALF, ///< Extract first 64 bits from 128 bit vector
LAST_SPUISD ///< Last user-defined instruction
};
}

6
lib/Target/CellSPU/SPUNodes.td
View File

@ -117,12 +117,6 @@ def SPUprefslot2vec: SDNode<"SPUISD::PREFSLOT2VEC", SDTprefslot2vec, []>;
def SPU_vec_demote : SDTypeProfile<1, 1, []>;
def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>;
def SPU_half_2_vec : SDTypeProfile<1, 1, []>;
def SPUhalf2vec: SDNode<"SPUISD::HALF2VEC", SPU_half_2_vec, []>;
def SPU_vec_2_half : SDTypeProfile<1, 1, []>;
def SPUvec2half: SDNode<"SPUISD::VEC2HALF", SPU_vec_2_half, []>;
// Address high and low components, used for [r+r] type addressing
def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;