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ARM assembly parsing for two-operand form of 'mul' instruction.

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rdar://10449856.

llvm-svn: 144689
This commit is contained in:
Jim Grosbach 2011-11-15 20:14:51 +00:00
parent 8b1d4c989c
commit f0690cd90c
2 changed files with 12 additions and 0 deletions
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6
lib/Target/ARM/ARMInstrVFP.td
View File

@ -1172,3 +1172,9 @@ defm : VFPDT64InstAlias<"vldr${p}", "$Dd, $addr",
(VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
defm : VFPDT64InstAlias<"vstr${p}", "$Dd, $addr",
(VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
// VMUL has a two-operand form (implied destination operand)
def : VFP2InstAlias<"vmul${p}.f64 $Dn, $Dm",
(VMULD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
def : VFP2InstAlias<"vmul${p}.f32 $Sn, $Sm",
(VMULS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;

6
test/MC/ARM/simple-fp-encoding.s
View File

@ -21,9 +21,15 @@
@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
vmul.f64 d16, d17, d16
@ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee]
vmul.f64 d20, d17
@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
vmul.f32 s0, s1, s0
@ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee]
vmul.f32 s11, s21
@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
vnmul.f64 d16, d17, d16