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StructurizeCFG,AMDGPU: Test case of a redundant phi and codegen consequences

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Change-Id: I9681f9e41ca30f82576f3d1f965c3a550a34b171
llvm-svn: 344569
This commit is contained in:
Nicolai Haehnle 2018-10-15 22:37:46 +00:00
parent 59a92dbf80
commit f0d5ff2644
2 changed files with 79 additions and 0 deletions
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34
test/CodeGen/AMDGPU/smrd.ll
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@ -535,6 +535,40 @@ exit:
}
; GCN-LABEL: {{^}}smrd_uniform_loop2:
; (this test differs from smrd_uniform_loop by the more complex structure of phis,
; which currently confuses the DivergenceAnalysis after structurization)
;
; TODO: this should use an s_buffer_load
;
; GCN: buffer_load_dword
define amdgpu_ps float @smrd_uniform_loop2(<4 x i32> inreg %desc, i32 %bound, i32 %bound.a) #0 {
main_body:
br label %loop
loop:
%counter = phi i32 [ 0, %main_body ], [ %counter.next, %loop.a ], [ %counter.next, %loop.b ]
%sum = phi float [ 0.0, %main_body ], [ %sum.next, %loop.a ], [ %sum.next.b, %loop.b ]
%offset = shl i32 %counter, 2
%v = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %offset)
%sum.next = fadd float %sum, %v
%counter.next = add i32 %counter, 1
%cc = icmp uge i32 %counter.next, %bound
br i1 %cc, label %exit, label %loop.a
loop.a:
%cc.a = icmp uge i32 %counter.next, %bound.a
br i1 %cc, label %loop, label %loop.b
loop.b:
%sum.next.b = fadd float %sum.next, 1.0
br label %loop
exit:
ret float %sum.next
}
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1
declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2

45
test/Transforms/StructurizeCFG/loop-continue-phi.ll Normal file
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@ -0,0 +1,45 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -o - -structurizecfg < %s | FileCheck %s
;
; TODO: eliminate redundant phis for the loop counter
;
define void @test1() {
; CHECK-LABEL: @test1(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: Flow:
; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[CTR_NEXT:%.*]], [[LOOP_B:%.*]] ], [ [[CTR_NEXT]], [[LOOP_A:%.*]] ]
; CHECK-NEXT: br label [[FLOW1:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[CTR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP1:%.*]], [[FLOW1]] ]
; CHECK-NEXT: [[CTR_NEXT]] = add i32 [[CTR]], 1
; CHECK-NEXT: br i1 undef, label [[LOOP_A]], label [[FLOW1]]
; CHECK: loop.a:
; CHECK-NEXT: br i1 undef, label [[LOOP_B]], label [[FLOW:%.*]]
; CHECK: loop.b:
; CHECK-NEXT: br label [[FLOW]]
; CHECK: Flow1:
; CHECK-NEXT: [[TMP1]] = phi i32 [ [[TMP0]], [[FLOW]] ], [ undef, [[LOOP]] ]
; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ false, [[FLOW]] ], [ true, [[LOOP]] ]
; CHECK-NEXT: br i1 [[TMP2]], label [[EXIT:%.*]], label [[LOOP]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop
loop:
%ctr = phi i32 [ 0, %entry ], [ %ctr.next, %loop.a ], [ %ctr.next, %loop.b ]
%ctr.next = add i32 %ctr, 1
br i1 undef, label %exit, label %loop.a
loop.a:
br i1 undef, label %loop, label %loop.b
loop.b:
br label %loop
exit:
ret void
}