Fixing improperly encoded reverse subtract instructions in MBlaze backend.

llvm-svn: 118943
This commit is contained in:
Wesley Peck 2010-11-12 23:41:10 +00:00
parent 053d9fb9b5
commit f11db049fe
3 changed files with 16 additions and 17 deletions

View File

@ -125,18 +125,17 @@ class TB<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
class TAR<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
list<dag> pattern, InstrItinClass itin> :
MBlazeInst<op,FRRR,outs, ins, asmstr, pattern, itin>
TA<op, flags, outs, ins, asmstr, pattern, itin>
{
bits<5> rd;
bits<5> rb;
bits<5> ra;
bits<5> rrd;
bits<5> rrb;
bits<5> rra;
let Form = FRRRR;
let Inst{6-10} = rd;
let Inst{11-15} = ra;
let Inst{16-20} = rb;
let Inst{21-31} = flags;
let rd = rrd;
let ra = rra;
let rb = rrb;
}
//===----------------------------------------------------------------------===//

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@ -177,7 +177,7 @@ class ShiftI<bits<6> op, bits<2> flags, string instr_asm, SDNode OpNode,
class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
InstrItinClass itin> :
TAR<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
!strconcat(instr_asm, " $dst, $c, $b"),
[(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;

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@ -81,24 +81,24 @@
# CHECK: encoding: [0x80,0x22,0x18,0x00]
or r1, r2, r3
# FIXMEC: rsub
# CHECK: rsub
# BINARY: 000001 00001 00010 00011 00000000000
# FIXMEC: encoding: [0x04,0x22,0x18,0x00]
# CHECK: encoding: [0x04,0x22,0x18,0x00]
rsub r1, r2, r3
# FIXMEC: rsubc
# CHECK: rsubc
# BINARY: 000011 00001 00010 00011 00000000000
# FIXMEC: encoding: [0x0c,0x22,0x18,0x00]
# CHECK: encoding: [0x0c,0x22,0x18,0x00]
rsubc r1, r2, r3
# FIXMEC: rsubk
# CHECK: rsubk
# BINARY: 000101 00001 00010 00011 00000000000
# FIXMEC: encoding: [0x14,0x22,0x18,0x00]
# CHECK: encoding: [0x14,0x22,0x18,0x00]
rsubk r1, r2, r3
# FIXMEC: rsubkc
# CHECK: rsubkc
# BINARY: 000111 00001 00010 00011 00000000000
# FIXMEC: encoding: [0x1c,0x22,0x18,0x00]
# CHECK: encoding: [0x1c,0x22,0x18,0x00]
rsubkc r1, r2, r3
# CHECK: sext16