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Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.

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llvm-svn: 154101
This commit is contained in:
Silviu Baranga 2012-04-05 16:19:29 +00:00
parent 1c2668f700
commit f376e00699
2 changed files with 21 additions and 4 deletions
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8
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1331,10 +1331,10 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
let Inst{4} = 0;
let Inst{3-0} = shift{3-0};
}
def rsr : AsI1<opcod, (outs GPR:$Rd),
(ins GPR:$Rn, so_reg_reg:$shift),
def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, so_reg_reg:$shift),
DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
[(set GPRnopc:$Rd, CPSR, (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
Requires<[IsARM]> {
bits<4> Rd;
bits<4> Rn;
@ -1368,7 +1368,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
cc_out:$s)>,
Requires<[IsARM]>;
def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
(!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
(!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPRnopc:$Rdn, GPRnopc:$Rdn,
so_reg_reg:$shift, pred:$p,
cc_out:$s)>,
Requires<[IsARM]>;

17
test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt Normal file
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@ -0,0 +1,17 @@
# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
# CHECK: potentially undefined
# CHECK: 0x1f 0x12 0xb0 0x00
0x1f 0x12 0xb0 0x00
# CHECK: potentially undefined
# CHECK: 0x13 0xf2 0xb0 0x00
0x13 0xf2 0xb0 0x00
# CHECK: potentially undefined
# CHECK: 0x13 0x1f 0xb0 0x00
0x13 0x1f 0xb0 0x00
# CHECK: potentially undefined
# CHECK: 0x13 0x12 0xbf 0x00
0x13 0x12 0xbf 0x00