[mips][msa] A small refactor to reduce patch noise in my next commit

No functional change. An if-statement has been split into two nested if-statements.

llvm-svn: 195972
This commit is contained in:
Daniel Sanders 2013-11-30 13:15:21 +00:00
parent 7150312963
commit f397466fb3

View File

@ -113,21 +113,23 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
// If MI is not a debug value, make sure Offset fits in the 16-bit immediate // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
// field. // field.
if (!MI.isDebugValue() && !isInt<16>(Offset)) { if (!MI.isDebugValue()) {
MachineBasicBlock &MBB = *MI.getParent(); if (!isInt<16>(Offset)) {
DebugLoc DL = II->getDebugLoc(); MachineBasicBlock &MBB = *MI.getParent();
unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; DebugLoc DL = II->getDebugLoc();
unsigned NewImm; unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
const MipsSEInstrInfo &TII = unsigned NewImm;
*static_cast<const MipsSEInstrInfo*>( const MipsSEInstrInfo &TII =
MBB.getParent()->getTarget().getInstrInfo()); *static_cast<const MipsSEInstrInfo *>(
unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm); MBB.getParent()->getTarget().getInstrInfo());
BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg) unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
.addReg(Reg, RegState::Kill); BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
.addReg(Reg, RegState::Kill);
FrameReg = Reg; FrameReg = Reg;
Offset = SignExtend64<16>(NewImm); Offset = SignExtend64<16>(NewImm);
IsKill = true; IsKill = true;
}
} }
MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);