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AMDGPU: Materialize sign bits with bfrev
If a constant is the same as the reverse of an inline immediate, this is 4 bytes smaller than having to embed a 32-bit literal. llvm-svn: 263201
This commit is contained in:
Matt Arsenault
parent
e115db8a26
commit
f422acdb0e
@ -226,6 +226,30 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
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continue;
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}
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if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {
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// If this has a literal constant source that is the same as the
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// reversed bits of an inline immediate, replace with a bitreverse of
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// that constant. This saves 4 bytes in the common case of materializing
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// sign bits.
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// Test if we are after regalloc. We only want to do this after any
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// optimizations happen because this will confuse them.
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// XXX - not exactly a check for post-regalloc run.
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MachineOperand &Src = MI.getOperand(1);
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if (Src.isImm() &&
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TargetRegisterInfo::isPhysicalRegister(MI.getOperand(0).getReg())) {
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int64_t Imm = Src.getImm();
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if (isInt<32>(Imm) && !TII->isInlineConstant(Src, 4)) {
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int32_t ReverseImm = reverseBits<int32_t>(static_cast<int32_t>(Imm));
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if (ReverseImm >= -16 && ReverseImm <= 64) {
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MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));
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Src.setImm(ReverseImm);
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continue;
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}
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}
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}
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}
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if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
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continue;
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158
test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
Normal file
158
test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll
Normal file
@ -0,0 +1,158 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Test that materialization constants that are the bit reversed of
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; inline immediates are replaced with bfrev of the inline immediate to
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; save code size.
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; GCN-LABEL: {{^}}materialize_0_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0{{$}}
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; GCN: buffer_store_dword [[K]]
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define void @materialize_0_i32(i32 addrspace(1)* %out) {
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_0_i64:
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; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
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; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], 0{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_0_i64(i64 addrspace(1)* %out) {
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store i64 0, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_neg1_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], -1{{$}}
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; GCN: buffer_store_dword [[K]]
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define void @materialize_neg1_i32(i32 addrspace(1)* %out) {
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store i32 -1, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_neg1_i64:
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; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
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; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], -1{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_neg1_i64(i64 addrspace(1)* %out) {
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store i64 -1, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_signbit_i32:
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; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}}
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; GCN: buffer_store_dword [[K]]
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define void @materialize_signbit_i32(i32 addrspace(1)* %out) {
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store i32 -2147483648, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_signbit_i64:
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; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
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; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_signbit_i64(i64 addrspace(1)* %out) {
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store i64 -9223372036854775808, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_neg16_i32:
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; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}}
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; GCN: buffer_store_dword [[K]]
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define void @materialize_rev_neg16_i32(i32 addrspace(1)* %out) {
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store i32 268435455, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_neg16_i64:
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; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
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; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_rev_neg16_i64(i64 addrspace(1)* %out) {
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store i64 1152921504606846975, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_neg17_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0xf7ffffff{{$}}
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; GCN: buffer_store_dword [[K]]
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define void @materialize_rev_neg17_i32(i32 addrspace(1)* %out) {
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store i32 -134217729, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_neg17_i64:
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; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0xf7ffffff{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_rev_neg17_i64(i64 addrspace(1)* %out) {
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store i64 -576460752303423489, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_64_i32:
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; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}}
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; GCN: buffer_store_dword [[K]]
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define void @materialize_rev_64_i32(i32 addrspace(1)* %out) {
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store i32 33554432, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_64_i64:
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; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
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; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_rev_64_i64(i64 addrspace(1)* %out) {
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store i64 144115188075855872, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_65_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x82000000{{$}}
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; GCN: buffer_store_dword [[K]]
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define void @materialize_rev_65_i32(i32 addrspace(1)* %out) {
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store i32 -2113929216, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_65_i64:
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; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0x82000000{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_rev_65_i64(i64 addrspace(1)* %out) {
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store i64 -9079256848778919936, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_3_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], -2.0{{$}}
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; GCN: buffer_store_dword [[K]]
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define void @materialize_rev_3_i32(i32 addrspace(1)* %out) {
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store i32 -1073741824, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_3_i64:
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; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], -2.0{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_rev_3_i64(i64 addrspace(1)* %out) {
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store i64 -4611686018427387904, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_1.0_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1fc{{$}}
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; GCN: buffer_store_dword [[K]]
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define void @materialize_rev_1.0_i32(i32 addrspace(1)* %out) {
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store i32 508, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}materialize_rev_1.0_i64:
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; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0x1fc{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}}
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define void @materialize_rev_1.0_i64(i64 addrspace(1)* %out) {
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store i64 508, i64 addrspace(1)* %out
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ret void
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}
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@ -1,5 +1,5 @@
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; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.maxnum.f32(float, float) #0
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declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #0
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@ -207,7 +207,7 @@ define void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind {
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; FUNC-LABEL: @constant_fold_fmax_f32_n0_p0
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
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; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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@ -221,7 +221,7 @@ define void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind {
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; FUNC-LABEL: @constant_fold_fmax_f32_n0_n0
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; SI-NOT: v_max_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
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; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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@ -1,5 +1,5 @@
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; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare float @llvm.minnum.f32(float, float) #0
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@ -206,7 +206,7 @@ define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind {
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; FUNC-LABEL: @constant_fold_fmin_f32_n0_p0
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; SI-NOT: v_min_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
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; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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@ -220,7 +220,7 @@ define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind {
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; FUNC-LABEL: @constant_fold_fmin_f32_n0_n0
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; SI-NOT: v_min_f32_e32
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; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
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; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
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; SI: buffer_store_dword [[REG]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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@ -44,7 +44,7 @@ define void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) {
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}
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; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f64:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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@ -57,7 +57,7 @@ define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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; FUNC-LABEL: {{^}}fneg_fabs_f64:
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; SI: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}
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; SI: s_load_dwordx2
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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; SI-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]]
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; SI-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
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; SI: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}}
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@ -69,7 +69,7 @@ define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
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}
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; FUNC-LABEL: {{^}}fneg_fabs_v2f64:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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; SI-NOT: 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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@ -81,7 +81,7 @@ define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in)
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}
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; FUNC-LABEL: {{^}}fneg_fabs_v4f64:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}}
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; SI-NOT: 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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@ -23,7 +23,7 @@ entry:
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; CHECK-LABEL: {{^}}store_imm_neg_0.0_i64:
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; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
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; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x80000000
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; CHECK-DAG: v_bfrev_b32_e32 v[[HI_VREG:[0-9]+]], 1{{$}}
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; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
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define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) {
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store i64 -9223372036854775808, i64 addrspace(1) *%out
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@ -31,7 +31,7 @@ define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) {
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}
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; CHECK-LABEL: {{^}}store_inline_imm_neg_0.0_i32:
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; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
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; CHECK: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
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; CHECK: buffer_store_dword [[REG]]
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define void @store_inline_imm_neg_0.0_i32(i32 addrspace(1)* %out) {
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store i32 -2147483648, i32 addrspace(1)* %out
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@ -47,7 +47,7 @@ define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
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}
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; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32:
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; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
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; CHECK: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
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; CHECK: buffer_store_dword [[REG]]
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define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) {
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store float -0.0, float addrspace(1)* %out
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@ -520,7 +520,7 @@ define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) {
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; CHECK-LABEL: {{^}}store_literal_imm_neg_0.0_f64:
|
||||
; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
|
||||
; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x80000000
|
||||
; CHECK-DAG: v_bfrev_b32_e32 v[[HI_VREG:[0-9]+]], 1{{$}}
|
||||
; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
|
||||
define void @store_literal_imm_neg_0.0_f64(double addrspace(1)* %out) {
|
||||
store double -0.0, double addrspace(1)* %out
|
||||
|
||||
Loading…
Reference in New Issue
Block a user