RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-26 06:04:47 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.

Browse Source 
rdar://10418009

llvm-svn: 144213
This commit is contained in:
Chad Rosier 2011-11-09 21:30:12 +00:00
parent ddc6bfa543
commit f47b941510
1 changed files with 13 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/ARM/ARMFastISel.cpp
View File

@ -846,9 +846,17 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
switch (VT.getSimpleVT().SimpleTy) {
default:
assert(false && "Unhandled load/store type!");
case MVT::i16:
if (isThumb2)
// Integer loads/stores handle 12-bit offsets.
needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
else
// ARM i16 integer loads/stores handle +/-imm8 offsets.
if (Addr.Offset > 255 || Addr.Offset < -255)
needsLowering = true;
break;
case MVT::i1:
case MVT::i8:
case MVT::i16:
case MVT::i32:
// Integer loads/stores handle 12-bit offsets.
needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
@ -932,14 +940,14 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
switch (VT.getSimpleVT().SimpleTy) {
// This is mostly going to be Neon/vector support.
default: return false;
case MVT::i16:
Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
RC = ARM::GPRRegisterClass;
break;
case MVT::i8:
Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12;
RC = ARM::GPRRegisterClass;
break;
case MVT::i16:
Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
RC = ARM::GPRRegisterClass;
break;
case MVT::i32:
Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
RC = ARM::GPRRegisterClass;