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https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-28 22:43:29 +00:00
Remove unneeded casts. No functionality change.
llvm-svn: 155800
This commit is contained in:
parent
2563aa98d4
commit
f526e691cf
@ -701,8 +701,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// First set operation action for all vector types to either promote
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// (for widening) or expand (for scalarization). Then we will selectively
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// turn on ones that can be effectively codegen'd.
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for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
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for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
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VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
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setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
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@ -760,8 +760,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
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for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
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for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
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InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
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setTruncStoreAction((MVT::SimpleValueType)VT,
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(MVT::SimpleValueType)InnerVT, Expand);
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setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
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@ -870,7 +870,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
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// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
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for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
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for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
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EVT VT = (MVT::SimpleValueType)i;
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// Do not attempt to custom lower non-power-of-2 vectors
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if (!isPowerOf2_32(VT.getVectorNumElements()))
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@ -899,7 +899,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
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for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
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for (int i = MVT::v16i8; i != MVT::v2i64; i++) {
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MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
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EVT VT = SVT;
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@ -1117,8 +1117,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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// Custom lower several nodes for 256-bit types.
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for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
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for (int i = MVT::FIRST_VECTOR_VALUETYPE;
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i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
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MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
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EVT VT = SVT;
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@ -1140,7 +1140,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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// Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
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for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
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for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
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MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
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EVT VT = SVT;
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@ -1163,8 +1163,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
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// of this type with custom code.
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for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
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for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
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VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
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setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
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Custom);
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}
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