mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-04 01:11:44 +00:00
Make MBB a class member instead of passing it around everywhere.
llvm-svn: 103925
This commit is contained in:
Jakob Stoklund Olesen
parent
e4766e6bda
commit
f5593b76bc
@ -58,6 +58,9 @@ namespace {
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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// Basic block currently being allocated.
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MachineBasicBlock *MBB;
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// StackSlotForVirtReg - Maps virtual regs to the frame index where these
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// values are spilled.
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IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
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@ -130,30 +133,29 @@ namespace {
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private:
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bool runOnMachineFunction(MachineFunction &Fn);
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void AllocateBasicBlock(MachineBasicBlock &MBB);
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void AllocateBasicBlock();
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int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
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bool isLastUseOfLocalReg(MachineOperand&);
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void addKillFlag(LiveRegMap::iterator i);
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void killVirtReg(LiveRegMap::iterator i);
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void killVirtReg(unsigned VirtReg);
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void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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LiveRegMap::iterator i, bool isKill);
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void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned VirtReg, bool isKill);
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void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator i,
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bool isKill);
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void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg,
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bool isKill);
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void usePhysReg(MachineOperand&);
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void definePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned PhysReg, RegState NewState);
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void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
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LiveRegMap::iterator assignVirtToPhysReg(unsigned VirtReg,
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unsigned PhysReg);
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LiveRegMap::iterator allocVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned VirtReg, unsigned Hint);
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unsigned defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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LiveRegMap::iterator allocVirtReg(MachineInstr *MI, unsigned VirtReg,
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unsigned Hint);
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unsigned defineVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg,
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unsigned Hint);
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unsigned reloadVirtReg(MachineInstr *MI,
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unsigned OpNum, unsigned VirtReg, unsigned Hint);
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unsigned reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned OpNum, unsigned VirtReg, unsigned Hint);
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void spillAll(MachineBasicBlock &MBB, MachineInstr *MI);
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void spillAll(MachineInstr *MI);
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void setPhysReg(MachineOperand &MO, unsigned PhysReg);
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};
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char RAFast::ID = 0;
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@ -233,19 +235,17 @@ void RAFast::killVirtReg(unsigned VirtReg) {
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/// spillVirtReg - This method spills the value specified by VirtReg into the
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/// corresponding stack slot if needed. If isKill is set, the register is also
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/// killed.
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void RAFast::spillVirtReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
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unsigned VirtReg, bool isKill) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Spilling a physical register is illegal!");
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LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
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assert(lri != LiveVirtRegs.end() && "Spilling unmapped virtual register");
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spillVirtReg(MBB, MI, lri, isKill);
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spillVirtReg(MI, lri, isKill);
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}
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/// spillVirtReg - Do the actual work of spilling.
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void RAFast::spillVirtReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
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LiveRegMap::iterator lri, bool isKill) {
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LiveReg &LR = lri->second;
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assert(PhysRegState[LR.PhysReg] == lri->first && "Broken RegState mapping");
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@ -259,10 +259,9 @@ void RAFast::spillVirtReg(MachineBasicBlock &MBB,
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DEBUG(dbgs() << "Spilling %reg" << lri->first
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<< " in " << TRI->getName(LR.PhysReg));
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const TargetRegisterClass *RC = MRI->getRegClass(lri->first);
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int FrameIndex = getStackSpaceFor(lri->first, RC);
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DEBUG(dbgs() << " to stack slot #" << FrameIndex << "\n");
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TII->storeRegToStackSlot(MBB, MI, LR.PhysReg, spillKill,
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FrameIndex, RC, TRI);
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int FI = getStackSpaceFor(lri->first, RC);
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DEBUG(dbgs() << " to stack slot #" << FI << "\n");
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TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, spillKill, FI, RC, TRI);
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++NumStores; // Update statistics
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if (spillKill)
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@ -279,14 +278,14 @@ void RAFast::spillVirtReg(MachineBasicBlock &MBB,
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}
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/// spillAll - Spill all dirty virtregs without killing them.
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void RAFast::spillAll(MachineBasicBlock &MBB, MachineInstr *MI) {
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void RAFast::spillAll(MachineInstr *MI) {
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SmallVector<unsigned, 16> Dirty;
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
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e = LiveVirtRegs.end(); i != e; ++i)
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if (i->second.Dirty)
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Dirty.push_back(i->first);
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for (unsigned i = 0, e = Dirty.size(); i != e; ++i)
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spillVirtReg(MBB, MI, Dirty[i], false);
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spillVirtReg(MI, Dirty[i], false);
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}
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/// usePhysReg - Handle the direct use of a physical register.
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@ -352,14 +351,14 @@ void RAFast::usePhysReg(MachineOperand &MO) {
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/// definePhysReg - Mark PhysReg as reserved or free after spilling any
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/// virtregs. This is very similar to defineVirtReg except the physreg is
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/// reserved instead of allocated.
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void RAFast::definePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned PhysReg, RegState NewState) {
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void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
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RegState NewState) {
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UsedInInstr.set(PhysReg);
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switch (unsigned VirtReg = PhysRegState[PhysReg]) {
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case regDisabled:
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break;
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default:
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spillVirtReg(MBB, MI, VirtReg, true);
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spillVirtReg(MI, VirtReg, true);
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// Fall through.
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case regFree:
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case regReserved:
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@ -376,7 +375,7 @@ void RAFast::definePhysReg(MachineBasicBlock &MBB, MachineInstr *MI,
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case regDisabled:
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break;
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default:
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spillVirtReg(MBB, MI, VirtReg, true);
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spillVirtReg(MI, VirtReg, true);
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// Fall through.
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case regFree:
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case regReserved:
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@ -402,8 +401,7 @@ RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
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}
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/// allocVirtReg - Allocate a physical register for VirtReg.
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RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
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MachineInstr *MI,
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RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI,
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unsigned VirtReg,
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unsigned Hint) {
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const unsigned spillCost = 100;
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@ -443,7 +441,7 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
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case regReserved:
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break;
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default:
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spillVirtReg(MBB, MI, PhysRegState[Hint], true);
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spillVirtReg(MI, PhysRegState[Hint], true);
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// Fall through.
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case regFree:
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return assignVirtToPhysReg(VirtReg, Hint);
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@ -520,7 +518,7 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
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// BestCost is 0 when all aliases are already disabled.
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if (BestCost) {
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if (PhysRegState[BestReg] != regDisabled)
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spillVirtReg(MBB, MI, PhysRegState[BestReg], true);
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spillVirtReg(MI, PhysRegState[BestReg], true);
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else {
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// Make sure all aliases are disabled.
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for (const unsigned *AS = TRI->getAliasSet(BestReg);
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@ -532,7 +530,7 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
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PhysRegState[Alias] = regDisabled;
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break;
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default:
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spillVirtReg(MBB, MI, PhysRegState[Alias], true);
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spillVirtReg(MI, PhysRegState[Alias], true);
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PhysRegState[Alias] = regDisabled;
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break;
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}
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@ -556,13 +554,13 @@ RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineBasicBlock &MBB,
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}
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/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
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unsigned RAFast::defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned OpNum, unsigned VirtReg, unsigned Hint) {
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unsigned RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
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unsigned VirtReg, unsigned Hint) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Not a virtual register");
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LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
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if (lri == LiveVirtRegs.end())
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lri = allocVirtReg(MBB, MI, VirtReg, Hint);
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lri = allocVirtReg(MI, VirtReg, Hint);
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else
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addKillFlag(lri); // Kill before redefine.
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LiveReg &LR = lri->second;
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@ -574,18 +572,18 @@ unsigned RAFast::defineVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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}
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/// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
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unsigned RAFast::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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unsigned OpNum, unsigned VirtReg, unsigned Hint) {
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unsigned RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
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unsigned VirtReg, unsigned Hint) {
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assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
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"Not a virtual register");
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LiveRegMap::iterator lri = LiveVirtRegs.find(VirtReg);
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if (lri == LiveVirtRegs.end()) {
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lri = allocVirtReg(MBB, MI, VirtReg, Hint);
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lri = allocVirtReg(MI, VirtReg, Hint);
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const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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DEBUG(dbgs() << "Reloading %reg" << VirtReg << " into "
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<< TRI->getName(lri->second.PhysReg) << "\n");
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TII->loadRegFromStackSlot(MBB, MI, lri->second.PhysReg, FrameIndex, RC,
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TII->loadRegFromStackSlot(*MBB, MI, lri->second.PhysReg, FrameIndex, RC,
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TRI);
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++NumLoads;
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} else if (lri->second.Dirty) {
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@ -614,25 +612,25 @@ void RAFast::setPhysReg(MachineOperand &MO, unsigned PhysReg) {
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MO.setReg(PhysReg);
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}
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void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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DEBUG(dbgs() << "\nAllocating " << MBB);
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void RAFast::AllocateBasicBlock() {
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DEBUG(dbgs() << "\nAllocating " << *MBB);
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atEndOfBlock = false;
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PhysRegState.assign(TRI->getNumRegs(), regDisabled);
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assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
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MachineBasicBlock::iterator MII = MBB.begin();
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MachineBasicBlock::iterator MII = MBB->begin();
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// Add live-in registers as live.
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for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(),
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E = MBB.livein_end(); I != E; ++I)
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definePhysReg(MBB, MII, *I, regReserved);
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for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
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definePhysReg(MII, *I, regReserved);
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SmallVector<unsigned, 8> VirtKills, PhysDefs;
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SmallVector<MachineInstr*, 32> Coalesced;
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// Otherwise, sequentially allocate each instruction in the MBB.
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while (MII != MBB.end()) {
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while (MII != MBB->end()) {
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MachineInstr *MI = MII++;
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const TargetInstrDesc &TID = MI->getDesc();
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DEBUG({
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@ -711,7 +709,7 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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if (MO.isUse()) {
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usePhysReg(MO);
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} else if (MO.isEarlyClobber()) {
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definePhysReg(MBB, MI, Reg, MO.isDead() ? regFree : regReserved);
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definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
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PhysDefs.push_back(Reg);
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}
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}
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@ -725,13 +723,13 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
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if (MO.isUse()) {
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unsigned PhysReg = reloadVirtReg(MBB, MI, i, Reg, CopyDst);
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unsigned PhysReg = reloadVirtReg(MI, i, Reg, CopyDst);
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CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
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setPhysReg(MO, PhysReg);
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if (MO.isKill())
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VirtKills.push_back(Reg);
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} else if (MO.isEarlyClobber()) {
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unsigned PhysReg = defineVirtReg(MBB, MI, i, Reg, 0);
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unsigned PhysReg = defineVirtReg(MI, i, Reg, 0);
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setPhysReg(MO, PhysReg);
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PhysDefs.push_back(PhysReg);
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}
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@ -763,11 +761,11 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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if (!Allocatable.test(Reg)) continue;
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definePhysReg(MBB, MI, Reg, (MO.isImplicit() || MO.isDead()) ?
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regFree : regReserved);
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definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
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regFree : regReserved);
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continue;
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}
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unsigned PhysReg = defineVirtReg(MBB, MI, i, Reg, CopySrc);
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unsigned PhysReg = defineVirtReg(MI, i, Reg, CopySrc);
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if (MO.isDead()) {
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VirtKills.push_back(Reg);
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CopyDst = 0; // cancel coalescing;
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@ -779,7 +777,7 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// Spill all dirty virtregs before a call, in case of an exception.
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if (TID.isCall()) {
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DEBUG(dbgs() << " Spilling remaining registers before call.\n");
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spillAll(MBB, MI);
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spillAll(MI);
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}
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// Process virtreg deads.
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@ -799,8 +797,8 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// Spill all physical registers holding virtual registers now.
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atEndOfBlock = true;
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MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
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if (MI != MBB.end() && MI->getDesc().isReturn()) {
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MachineBasicBlock::iterator MI = MBB->getFirstTerminator();
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if (MI != MBB->end() && MI->getDesc().isReturn()) {
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// This is a return block, kill all virtual registers.
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DEBUG(dbgs() << "Killing live registers at end of return block.\n");
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
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@ -811,17 +809,17 @@ void RAFast::AllocateBasicBlock(MachineBasicBlock &MBB) {
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DEBUG(dbgs() << "Spilling live registers at end of block.\n");
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for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
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i != e; ++i)
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spillVirtReg(MBB, MI, i, true);
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spillVirtReg(MI, i, true);
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}
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LiveVirtRegs.clear();
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// Erase all the coalesced copies. We are delaying it until now because
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// LiveVirtsRegs might refer to the instrs.
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for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
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MBB.erase(Coalesced[i]);
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MBB->erase(Coalesced[i]);
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NumCopies += Coalesced.size();
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DEBUG(MBB.dump());
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DEBUG(MBB->dump());
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}
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/// runOnMachineFunction - Register allocate the whole function
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@ -847,9 +845,11 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
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StackSlotForVirtReg.grow(LastVirtReg);
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// Loop over all of the basic blocks, eliminating virtual register references
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB)
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AllocateBasicBlock(*MBB);
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for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
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MBBi != MBBe; ++MBBi) {
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MBB = &*MBBi;
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AllocateBasicBlock();
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}
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// Make sure the set of used physregs is closed under subreg operations.
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MRI->closePhysRegsUsed(*TRI);
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