RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-09 05:47:13 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[Hexagon] Avoid creating 5-instruction packets with vgather pseudos

Browse Source 
Change the resource usage of the vgather pseudos from SLOT0+LD to
SLOT0+SLOT1.

llvm-svn: 355524
This commit is contained in:
Krzysztof Parzyszek 2019-03-06 17:43:50 +00:00
parent eb6ccfc75e
commit f565f6bfc6
2 changed files with 29 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/Hexagon/HexagonIICHVX.td
View File

@ -16,12 +16,14 @@ class HVXItin {
InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>],
[9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>,
// Used by Gather Pseudo Instructions which are expanded into
// V6_vgather* and V6_vS32b_new_ai. Even though these instructions
// use CVI_ST resource, it's not included below to avoid having more than
// 4 InstrStages and thus changing 'MaxResTerms' to 5.
// Used by gather pseudo-instructions which are expanded into V6_vgather*
// and V6_vS32b_new_ai. Even though these instructions use CVI_LD resource,
// it's not included below to avoid having more than 4 InstrStages and
// thus changing 'MaxResTerms' to 5. Instead, both SLOT0 and SLOT1 are
// used, which should be sufficient.
InstrItinData <CVI_GATHER_PSEUDO,
[InstrStage<1, [SLOT0], 0>,
InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [SLOT1], 0>,
InstrStage<1, [CVI_ST], 0>,
InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>];
}

22
test/CodeGen/Hexagon/packetize-vgather-slot01.mir Normal file
View File

@ -0,0 +1,22 @@
# RUN: llc -march=hexagon -mcpu=hexagonv65 -mattr=+hvxv65,+hvx-length64b -run-pass=hexagon-packetizer -o - %s | FileCheck %s
# Check that we don't generate a packet with 5 instructions.
# CHECK: BUNDLE
# CHECK-NEXT: V6_vaslw_acc
# CHECK-NEXT: V6_vgathermw
# CHECK-NEXT: V6_vS32b_new_ai
# CHECK-NEXT: A2_addi
# CHECK-NEXT: }
name: fred
tracksRegLiveness: true
body: |
bb.0:
liveins: $r0, $r1, $r2, $r3, $m0, $v0, $v1, $v2
$v0 = V6_vaslw_acc $v0, killed $v1, $r0
V6_vgathermw_pseudo $r1, $r2, $m0, killed $v2
$r4 = A2_addi $r1, 512
$r5 = A2_addi $r1, 640
V6_vgathermw_pseudo killed $r3, $r2, $m0, killed $v0
...