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R600: Do not fold single instruction with more that 3 kcache read
It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175183
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@ -334,6 +334,8 @@ bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
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SDValue Operand = Ops[OperandIdx[i] - 1];
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switch (Operand.getOpcode()) {
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case AMDGPUISD::CONST_ADDRESS: {
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if (i == 2)
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break;
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SDValue CstOffset;
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if (!Operand.getValueType().isVector() &&
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SelectGlobalValueConstantOffset(Operand.getOperand(0), CstOffset)) {
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@ -180,7 +180,7 @@ bool R600LowerConstCopy::runOnMachineFunction(MachineFunction &MF) {
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int ConstMovSel =
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TII->getOperandIdx(CstMov->getOpcode(), R600Operands::SRC0_SEL);
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unsigned ConstIndex = CstMov->getOperand(ConstMovSel).getImm();
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if (canFoldInBundle(CP, ConstIndex)) {
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if (MI->isInsideBundle() && canFoldInBundle(CP, ConstIndex)) {
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TII->setImmOperand(MI, OpTable[SrcOp][1], ConstIndex);
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MI->getOperand(SrcIdx).setReg(AMDGPU::ALU_CONST);
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} else {
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52
test/CodeGen/R600/kcache-fold.ll
Normal file
52
test/CodeGen/R600/kcache-fold.ll
Normal file
@ -0,0 +1,52 @@
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;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; CHECK: MOV T{{[0-9]+\.[XYZW], CBuf0\[[0-9]+\]\.[XYZW]}}
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define void @main() {
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main_body:
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%0 = load <4 x float> addrspace(9)* null
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%1 = extractelement <4 x float> %0, i32 0
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%2 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
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%3 = extractelement <4 x float> %2, i32 0
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%4 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
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%5 = extractelement <4 x float> %4, i32 0
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%6 = fcmp ult float %1, 0.000000e+00
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%7 = select i1 %6, float %3, float %5
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%8 = load <4 x float> addrspace(9)* null
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%9 = extractelement <4 x float> %8, i32 1
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%10 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
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%11 = extractelement <4 x float> %10, i32 1
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%12 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
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%13 = extractelement <4 x float> %12, i32 1
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%14 = fcmp ult float %9, 0.000000e+00
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%15 = select i1 %14, float %11, float %13
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%16 = load <4 x float> addrspace(9)* null
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%17 = extractelement <4 x float> %16, i32 2
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%18 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
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%19 = extractelement <4 x float> %18, i32 2
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%20 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
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%21 = extractelement <4 x float> %20, i32 2
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%22 = fcmp ult float %17, 0.000000e+00
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%23 = select i1 %22, float %19, float %21
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%24 = load <4 x float> addrspace(9)* null
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%25 = extractelement <4 x float> %24, i32 3
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%26 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1)
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%27 = extractelement <4 x float> %26, i32 3
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%28 = load <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2)
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%29 = extractelement <4 x float> %28, i32 3
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%30 = fcmp ult float %25, 0.000000e+00
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%31 = select i1 %30, float %27, float %29
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%32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00)
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%33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00)
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%34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00)
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%35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00)
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%36 = insertelement <4 x float> undef, float %32, i32 0
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%37 = insertelement <4 x float> %36, float %33, i32 1
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%38 = insertelement <4 x float> %37, float %34, i32 2
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%39 = insertelement <4 x float> %38, float %35, i32 3
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call void @llvm.R600.store.swizzle(<4 x float> %39, i32 0, i32 0)
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ret void
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}
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declare float @llvm.AMDIL.clamp.(float, float, float) readnone
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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