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[llvm-mca] Use an ordered map to collect hardware statistics. NFC.

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Histogram entries are now ordered by key.  This should improves their
readability when statistics are printed.

llvm-svn: 334961
This commit is contained in:
Andrea Di Biagio 2018-06-18 17:04:56 +00:00
parent 168f8d1e75
commit f6e62b21be
10 changed files with 17 additions and 14 deletions
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1
test/tools/llvm-mca/X86/BtVer2/partial-reg-update-2.s
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@ -1,3 +1,4 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
imul %rax, %rbx

2
test/tools/llvm-mca/X86/BtVer2/register-files-2.s
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@ -22,8 +22,8 @@ vmulps %xmm0, %xmm0, %xmm0
# CHECK: Dispatch Logic - number of cycles where we saw N instructions dispatched:
# CHECK-NEXT: [# dispatched], [# cycles]
# CHECK-NEXT: 0, 20 (71.4%)
# CHECK-NEXT: 2, 2 (7.1%)
# CHECK-NEXT: 1, 6 (21.4%)
# CHECK-NEXT: 2, 2 (7.1%)
# CHECK: Register File statistics:
# CHECK-NEXT: Total number of mappings created: 10

2
test/tools/llvm-mca/X86/option-all-stats-1.s
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@ -35,8 +35,8 @@ add %eax, %eax
# FULLREPORT: Dispatch Logic - number of cycles where we saw N instructions dispatched:
# FULLREPORT-NEXT: [# dispatched], [# cycles]
# FULLREPORT-NEXT: 0, 22 (21.4%)
# FULLREPORT-NEXT: 2, 19 (18.4%)
# FULLREPORT-NEXT: 1, 62 (60.2%)
# FULLREPORT-NEXT: 2, 19 (18.4%)
# FULLREPORT: Schedulers - number of cycles where we saw N instructions issued:
# FULLREPORT-NEXT: [# issued], [# cycles]

2
test/tools/llvm-mca/X86/option-all-stats-2.s
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@ -36,8 +36,8 @@ add %eax, %eax
# FULL: Dispatch Logic - number of cycles where we saw N instructions dispatched:
# FULL-NEXT: [# dispatched], [# cycles]
# FULL-NEXT: 0, 22 (21.4%)
# FULL-NEXT: 2, 19 (18.4%)
# FULL-NEXT: 1, 62 (60.2%)
# FULL-NEXT: 2, 19 (18.4%)
# FULL: Schedulers - number of cycles where we saw N instructions issued:
# FULL-NEXT: [# issued], [# cycles]

2
test/tools/llvm-mca/X86/option-all-views-1.s
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@ -37,8 +37,8 @@ add %eax, %eax
# FULLREPORT: Dispatch Logic - number of cycles where we saw N instructions dispatched:
# FULLREPORT-NEXT: [# dispatched], [# cycles]
# FULLREPORT-NEXT: 0, 22 (21.4%)
# FULLREPORT-NEXT: 2, 19 (18.4%)
# FULLREPORT-NEXT: 1, 62 (60.2%)
# FULLREPORT-NEXT: 2, 19 (18.4%)
# FULLREPORT: Schedulers - number of cycles where we saw N instructions issued:
# FULLREPORT-NEXT: [# issued], [# cycles]

2
test/tools/llvm-mca/X86/option-all-views-2.s
View File

@ -36,8 +36,8 @@ add %eax, %eax
# ALL: Dispatch Logic - number of cycles where we saw N instructions dispatched:
# ALL-NEXT: [# dispatched], [# cycles]
# ALL-NEXT: 0, 22 (21.4%)
# ALL-NEXT: 2, 19 (18.4%)
# ALL-NEXT: 1, 62 (60.2%)
# ALL-NEXT: 2, 19 (18.4%)
# ALL: Schedulers - number of cycles where we saw N instructions issued:
# ALL-NEXT: [# issued], [# cycles]

4
tools/llvm-mca/DispatchStatistics.h
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@ -35,9 +35,9 @@
#define LLVM_TOOLS_LLVM_MCA_DISPATCHVIEW_H
#include "View.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include <map>
namespace mca {
@ -49,7 +49,7 @@ class DispatchStatistics : public View {
// is one counter for every generic stall kind (see class HWStallEvent).
llvm::SmallVector<unsigned, 8> HWStalls;
using Histogram = llvm::DenseMap<unsigned, unsigned>;
using Histogram = std::map<unsigned, unsigned>;
Histogram DispatchGroupSizePerCycle;
void updateHistograms() {

4
tools/llvm-mca/RetireControlUnitStatistics.h
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@ -27,13 +27,13 @@
#define LLVM_TOOLS_LLVM_MCA_RETIRECONTROLUNITSTATISTICS_H
#include "View.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include <map>
namespace mca {
class RetireControlUnitStatistics : public View {
using Histogram = llvm::DenseMap<unsigned, unsigned>;
using Histogram = std::map<unsigned, unsigned>;
Histogram RetiredPerCycle;
unsigned NumRetired;

6
tools/llvm-mca/SchedulerStatistics.cpp
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@ -81,8 +81,10 @@ void SchedulerStatistics::printSchedulerUsage(raw_ostream &OS) const {
if (ProcResource.BufferSize <= 0)
continue;
const BufferUsage &BU = BufferedResources.lookup(I);
TempStream << ProcResource.Name << ", " << BU.MaxUsedSlots << '/'
const auto It = BufferedResources.find(I);
unsigned MaxUsedSlots =
It == BufferedResources.end() ? 0 : It->second.MaxUsedSlots;
TempStream << ProcResource.Name << ", " << MaxUsedSlots << '/'
<< ProcResource.BufferSize << '\n';
}

6
tools/llvm-mca/SchedulerStatistics.h
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@ -33,15 +33,15 @@
#include "View.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include <map>
namespace mca {
class SchedulerStatistics : public View {
const llvm::MCSchedModel &SM;
using Histogram = llvm::DenseMap<unsigned, unsigned>;
using Histogram = std::map<unsigned, unsigned>;
Histogram IssuedPerCycle;
unsigned NumIssued;
@ -53,7 +53,7 @@ class SchedulerStatistics : public View {
unsigned MaxUsedSlots;
};
llvm::DenseMap<unsigned, BufferUsage> BufferedResources;
std::map<unsigned, BufferUsage> BufferedResources;
void updateHistograms() {
IssuedPerCycle[NumIssued]++;