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Fix incorrect check for sign-extended constant BUILD_VECTOR.
<rdar://problem/10298332> llvm-svn: 142371
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@ -4527,7 +4527,7 @@ static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
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unsigned HalfSize = EltSize / 2;
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if (isSigned) {
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int64_t SExtVal = C->getSExtValue();
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if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
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if (SExtVal != SExtVal << (64 - HalfSize) >> (64 - HalfSize))
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return false;
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} else {
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if ((C->getZExtValue() >> HalfSize) != 0)
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@ -514,3 +514,14 @@ entry:
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store <8 x i8> %10, <8 x i8>* %11, align 8
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ret void
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}
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; If one operand has a zero-extend and the other a sign-extend, vmull
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; cannot be used.
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define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {
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; CHECK: vmullWithInconsistentExtensions
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; CHECK-NOT: vmull.s8
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%1 = sext <8 x i8> %vec to <8 x i16>
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%2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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%3 = extractelement <8 x i16> %2, i32 0
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ret i16 %3
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}
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