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[mips] Make isel select the correct DEXT variant up front.

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Summary:
Previously, it would always select DEXT and substitute any invalid matches
for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works
but causes problems when adding range checked immediates to IAS.

Now isel selects the correct variant up front.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D16810

llvm-svn: 262229
This commit is contained in:
Daniel Sanders 2016-02-29 15:26:54 +00:00
parent 9616254425
commit f80bcb1cba
10 changed files with 58 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -81,16 +81,10 @@ static void LowerLargeShift(MCInst& Inst) {
}
}
// Pick a DEXT or DINS instruction variant based on the pos and size operands
static void LowerDextDins(MCInst& InstIn) {
int Opcode = InstIn.getOpcode();
if (Opcode == Mips::DEXT)
assert(InstIn.getNumOperands() == 4 &&
"Invalid no. of machine operands for DEXT!");
else // Only DEXT and DINS are possible
assert(InstIn.getNumOperands() == 5 &&
"Invalid no. of machine operands for DINS!");
// Pick a DINS instruction variant based on the pos and size operands
static void LowerDins(MCInst& InstIn) {
assert(InstIn.getNumOperands() == 5 &&
"Invalid no. of machine operands for DINS!");
assert(InstIn.getOperand(2).isImm());
int64_t pos = InstIn.getOperand(2).getImm();
@ -98,17 +92,17 @@ static void LowerDextDins(MCInst& InstIn) {
int64_t size = InstIn.getOperand(3).getImm();
if (size <= 32) {
if (pos < 32) // DEXT/DINS, do nothing
if (pos < 32) // DINS, do nothing
return;
// DEXTU/DINSU
// DINSU
InstIn.getOperand(2).setImm(pos - 32);
InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
InstIn.setOpcode(Mips::DINSU);
return;
}
// DEXTM/DINSM
assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
// DINSM
assert(pos < 32 && "DINS cannot have both size and pos > 32");
InstIn.getOperand(3).setImm(size - 32);
InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
InstIn.setOpcode(Mips::DINSM);
return;
}
@ -164,9 +158,8 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
LowerLargeShift(TmpInst);
break;
// Double extract instruction is chosen by pos and size operands
case Mips::DEXT:
case Mips::DINS:
LowerDextDins(TmpInst);
LowerDins(TmpInst);
}
unsigned long N = Fixups.size();

2
lib/Target/Mips/MicroMips64r6InstrInfo.td
View File

@ -71,7 +71,7 @@ class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
// TODO: Add 'pos + size' constraint check to dext* instructions
// DEXT: 0 < pos + size <= 63
// DEXTM, DEXTU: 32 < pos + size <= 64
class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5,
class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6,
uimm5_plus1, MipsExt>;
class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
uimm5_plus33, MipsExt>;

6
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -845,10 +845,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1,
MipsExt>, EXT_FM_MM<0x2c>;
def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>;
def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
MipsIns>, EXT_FM_MM<0x0c>;
MipsIns>, EXT_FM_MM<0x0c>;
/// Jump Instructions
let DecoderMethod = "DecodeJumpTargetMM" in {

15
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -268,15 +268,14 @@ let isCodeGenOnly = 1 in
def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
let AdditionalPredicates = [NotInMicroMips] in {
// TODO: Add 'pos + size' constraint check to dext* instructions
// DEXT: 0 < pos + size <= 63
// DEXTM, DEXTU: 32 < pos + size <= 64
def DEXT : ExtBase<"dext", GPR64Opnd, uimm5, uimm5_plus1, MipsExt>,
EXT_FM<3>;
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, MipsExt>,
EXT_FM<1>;
// The 'pos + size' constraints are enforced by the code that lowers into
// MipsISD::Ext.
def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1,
immZExt5, immZExt5Plus1, MipsExt>, EXT_FM<3>;
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5,
immZExt5Plus33, MipsExt>, EXT_FM<1>;
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
MipsExt>, EXT_FM<2>;
immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>;
def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, MipsIns>,
EXT_FM<7>;
def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>,

26
lib/Target/Mips/MipsInstrInfo.td
View File

@ -653,6 +653,13 @@ def uimm16_64_relaxed : Operand<i64> {
!cast<AsmOperandClass>("UImm16RelaxedAsmOperandClass");
}
// Like uimm5 but reports a less confusing error for 32-63 when
// an instruction alias permits that.
def uimm5_report_uimm6 : Operand<i32> {
let PrintMethod = "printUnsignedImm";
let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;
}
// Like uimm5_64 but reports a less confusing error for 32-63 when
// an instruction alias permits that.
def uimm5_64_report_uimm6 : Operand<i64> {
@ -825,6 +832,16 @@ def immLow16Zero : PatLeaf<(imm), [{
// shamt field must fit in 5 bits.
def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
def immZExt5Plus1 : PatLeaf<(imm), [{
return isUInt<5>(N->getZExtValue() - 1);
}]>;
def immZExt5Plus32 : PatLeaf<(imm), [{
return isUInt<5>(N->getZExtValue() - 32);
}]>;
def immZExt5Plus33 : PatLeaf<(imm), [{
return isUInt<5>(N->getZExtValue() - 33);
}]>;
// True if (N + 1) fits in 16-bit field.
def immSExt16Plus1 : PatLeaf<(imm), [{
return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
@ -1273,10 +1290,11 @@ class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
// Ext and Ins
class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
Operand SizeOpnd, SDPatternOperator Op = null_frag> :
Operand SizeOpnd, PatFrag PosImm, PatFrag SizeImm,
SDPatternOperator Op = null_frag> :
InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
!strconcat(opstr, " $rt, $rs, $pos, $size"),
[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
[(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT,
FrmR, opstr>, ISA_MIPS32R2;
class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
@ -1763,8 +1781,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
}
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, MipsExt>,
EXT_FM<0>;
def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
immZExt5Plus1, MipsExt>, EXT_FM<0>;
def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1, MipsIns>,
EXT_FM<4>;

2
test/CodeGen/Mips/fcopysign-f32-f64.ll
View File

@ -18,7 +18,7 @@ entry:
; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]]
; 64: mtc1 $[[OR]], $f0
; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
; 64R2: mtc1 $[[INS]], $f0

2
test/CodeGen/Mips/fcopysign.ll
View File

@ -27,7 +27,7 @@ entry:
; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
; 64: dmtc1 $[[OR]], $f0
; 64R2: dext $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1
; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1
; 64R2: dmtc1 $[[INS]], $f0

10
test/CodeGen/Mips/mips64extins.ll
View File

@ -2,6 +2,7 @@
define i64 @dext(i64 %i) nounwind readnone {
entry:
; CHECK-LABEL: dext:
; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
%shr = lshr i64 %i, 5
%and = and i64 %shr, 1023
@ -10,7 +11,8 @@ entry:
define i64 @dextm(i64 %i) nounwind readnone {
entry:
; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
; CHECK-LABEL: dextm:
; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
%shr = lshr i64 %i, 5
%and = and i64 %shr, 17179869183
ret i64 %and
@ -18,7 +20,8 @@ entry:
define i64 @dextu(i64 %i) nounwind readnone {
entry:
; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
; CHECK-LABEL: dextu:
; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
%shr = lshr i64 %i, 34
%and = and i64 %shr, 63
ret i64 %and
@ -26,6 +29,7 @@ entry:
define i64 @dins(i64 %i, i64 %j) nounwind readnone {
entry:
; CHECK-LABEL: dins:
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
%shl2 = shl i64 %j, 8
%and = and i64 %shl2, 261888
@ -36,6 +40,7 @@ entry:
define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
entry:
; CHECK-LABEL: dinsm:
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33
%shl4 = shl i64 %j, 10
%and = and i64 %shl4, 8796093021184
@ -46,6 +51,7 @@ entry:
define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
entry:
; CHECK-LABEL: dinsu:
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
%shl4 = shl i64 %j, 40
%and = and i64 %shl4, 9006099743113216

4
test/MC/Mips/micromips64r6/invalid.s
View File

@ -19,8 +19,8 @@
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
# FIXME: Check various 'pos + size' constraints on dext*
dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
dext $2, $3, 32, 1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate

4
test/MC/Mips/mips64r2/invalid.s
View File

@ -9,8 +9,8 @@
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
# FIXME: Check various 'pos + size' constraints on dext*
dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
dext $2, $3, 32, 1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 32
dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate