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Implement r160312 as target indepedenet dag combine.

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llvm-svn: 160354
This commit is contained in:
Evan Cheng 2012-07-17 08:31:11 +00:00
parent 222d23f966
commit f84dd0cf40
4 changed files with 34 additions and 53 deletions
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27
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -2342,6 +2342,33 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
}
}
} else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
Cond == ISD::SETULE || Cond == ISD::SETUGT) {
bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
// X < 0x100000000 -> (X >> 32) < 1
// X >= 0x100000000 -> (X >> 32) >= 1
// X <= 0x0ffffffff -> (X >> 32) < 1
// X > 0x0ffffffff -> (X >> 32) >= 1
unsigned ShiftBits;
APInt NewC = C1;
ISD::CondCode NewCond = Cond;
if (AdjOne) {
ShiftBits = C1.countTrailingOnes();
NewC = NewC + 1;
NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
} else {
ShiftBits = C1.countTrailingZeros();
}
NewC = NewC.lshr(ShiftBits);
if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
EVT ShiftTy = DCI.isBeforeLegalize() ?
getPointerTy() : getShiftAmountTy(N0.getValueType());
EVT CmpTy = N0.getValueType();
SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
DAG.getConstant(ShiftBits, ShiftTy));
SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
}
}
}
}

44
lib/Target/X86/X86ISelLowering.cpp
View File

@ -3059,50 +3059,6 @@ static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
RHS = DAG.getConstant(0, RHS.getValueType());
return X86::COND_LE;
}
if (SetCCOpcode == ISD::SETULT || SetCCOpcode == ISD::SETUGE) {
unsigned TrailZeros = RHSC->getAPIntValue().countTrailingZeros();
if (TrailZeros >= 32) {
// The constant doesn't fit in cmp immediate field. Right shift LHS by
// the # of trailing zeros and truncate it to 32-bit. Then compare
// against shifted RHS.
assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!");
DebugLoc dl = LHS.getDebugLoc();
LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
DAG.getNode(ISD::SRL, dl, MVT::i64, LHS,
DAG.getConstant(TrailZeros, MVT::i8)));
uint64_t C = RHSC->getZExtValue() >> TrailZeros;
if (SetCCOpcode == ISD::SETULT) {
// X < 0x300000000 -> (X >> 32) < 3
// X < 0x100000000 -> (X >> 32) == 0
// X < 0x200000000 -> (X >> 33) == 0
if (C == 1) {
RHS = DAG.getConstant(0, MVT::i32);
return X86::COND_E;
}
RHS = DAG.getConstant(C, MVT::i32);
return X86::COND_B;
} else /* SetCCOpcode == ISD::SETUGE */ {
// X >= 0x100000000 -> (X >> 32) >= 1
RHS = DAG.getConstant(C, MVT::i32);
return X86::COND_AE;
}
}
}
if (SetCCOpcode == ISD::SETUGT) {
unsigned TrailOnes = RHSC->getAPIntValue().countTrailingOnes();
if (TrailOnes >= 32 && !RHSC->isAllOnesValue()) {
assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!");
DebugLoc dl = LHS.getDebugLoc();
LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
DAG.getNode(ISD::SRL, dl, MVT::i64, LHS,
DAG.getConstant(TrailOnes, MVT::i8)));
uint64_t C = (RHSC->getZExtValue()+1) >> TrailOnes;
// X > 0x0ffffffff -> (X >> 32) >= 1
RHS = DAG.getConstant(C, MVT::i32);
return X86::COND_AE;
}
}
}
switch (SetCCOpcode) {

6
test/CodeGen/CellSPU/icmp32.ll
View File

@ -322,10 +322,8 @@ entry:
define i32 @icmp_ult_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
; CHECK: icmp_ult_immed04_i32:
; CHECK: ila
; CHECK: ceq
; CHECK: clgt
; CHECK: nor
; CHECK: rotmi
; CHECK: ceqi
; CHECK: selb $3, $5, $4, $3
entry:

10
test/CodeGen/X86/cmp.ll
View File

@ -96,7 +96,7 @@ entry:
; CHECK: test7:
; CHECK-NOT: movabsq
; CHECK: shrq $32, %rdi
; CHECK: testl %edi, %edi
; CHECK: testq %rdi, %rdi
; CHECK: sete
%lnot = icmp ult i64 %res, 4294967296
%lnot.ext = zext i1 %lnot to i32
@ -108,7 +108,7 @@ entry:
; CHECK: test8:
; CHECK-NOT: movabsq
; CHECK: shrq $32, %rdi
; CHECK: cmpl $3, %edi
; CHECK: cmpq $3, %rdi
%lnot = icmp ult i64 %res, 12884901888
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext
@ -119,7 +119,7 @@ entry:
; CHECK: test9:
; CHECK-NOT: movabsq
; CHECK: shrq $33, %rdi
; CHECK: testl %edi, %edi
; CHECK: testq %rdi, %rdi
; CHECK: sete
%lnot = icmp ult i64 %res, 8589934592
%lnot.ext = zext i1 %lnot to i32
@ -131,8 +131,8 @@ entry:
; CHECK: test10:
; CHECK-NOT: movabsq
; CHECK: shrq $32, %rdi
; CHECK: cmpl $1, %edi
; CHECK: setae
; CHECK: testq %rdi, %rdi
; CHECK: setne
%lnot = icmp uge i64 %res, 4294967296
%lnot.ext = zext i1 %lnot to i32
ret i32 %lnot.ext